CY7C4281V CYPRESS [Cypress Semiconductor], CY7C4281V Datasheet - Page 2

• Manufacturer Part Number: CY7C4281V
• Description: 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06013 Rev. *A
Selection Guide
Pin Definitions
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply
Current (I
Density
Package
D
Q
WEN1
WEN2/LD
Dual Mode Pin
REN1, REN2
WCLK
RCLK
EF
FF
PAE
PAF
RS
OE
Signal Name
0 8
0 8
CC1
)
Data Inputs
Data Outputs
Write Enable 1
Write Enable 2
Load
Read Enable
Inputs
Write Clock
Read Clock
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
Description
32-pin PLCC
CY7C4261V
16K x 9
Commercial
Industrial
I/O
O Data Outputs for 9-bit bus.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
I
I
I
I
I
I
I
I
Data Inputs for 9-bit bus.
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is
HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
Enables the device for Read operation. Both REN1 and REN2 must be asserted to
allow a read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO are not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable
flag-offset register.
programmed into the FIFO. PAE is synchronized to RCLK.
programmed into the FIFO. PAF is synchronized to WCLK.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
7C4261/71/81/91V-10
32-pin PLCC
CY7C4271V
100
3.5
10
25
8
0
8
32K x 9
7C4261/71/81/91V-15
66.7
Description
15
10
10
25
30
32-pin PLCC
4
0
CY7C4281V
64K x 9
CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V
7C4261/71/81/91V-25
40
15
25
15
25
6
1
32-pin PLCC
CY7C4291V
128K x 9
Page 2 of 16
MHz
Unit
mA
ns
ns
ns
ns
ns