PLL102-108XC PLL [PhaseLink Corporation], PLL102-108XC Datasheet - Page 6

• Manufacturer Part Number: PLL102-108XC
• Description: Programmable DDR Zero Delay Clock Driver
• Manufacturer: PLL [PhaseLink Corporation]

TABLE 3: Output Drive Strength Programming Summary:
5. Byte 4: Buffer Drive Strength Control Register
6. Byte 5: Buffer Drive Strength Control Register
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Bit<2:0>
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
111
110
101
100
011
010
001
000
Strength
Strength
Strength
Strength
DDRA
DDRB
DDRC
DDRD
Programming Setting
Default
Name
Name
+40%
+30%
+20%
+10%
-10%
-20%
-30%
-
-
-
-
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Setting applies to the following outputs
1. DDRA (CLK0, CLK1, CLK5)
2. DDRB (CLK7, CLK8, CLK9)
3. DDRC (CLK2, CLK3, CLK4)
4. DDRD (CLK6)
5.
FBOUT
Default
Default
Programmable DDR Zero Delay Clock Driver
1
1
0
1
1
0
1
1
1
1
0
1
1
0
1
1
Reserved.
Reserved.
These three bits will program drive strength for CLK0, CLK1 and
CLK5 output clocks (see Table 3).
These three bits will program drive strength for CLK7, CLK8 and
CLK9 output clocks (see Table 3).
Reserved.
Reserved.
These three bits will program drive strength for CLK2, CLK3 and
CLK4 output clocks (see Table 3).
These three bits will program drive strength for CLK6 output clock
(see Table 3).
Description
Description
PLL102-108
Rev 03/29/02 Page 6