CY7C65620_1105 CYPRESS [Cypress Semiconductor], CY7C65620_1105 Datasheet - Page 5

• Manufacturer Part Number: CY7C65620_1105
• Description: EZ-USB HX2LP Low Power USB 2.0 Hub Controller Family
• Manufacturer: CYPRESS [Cypress Semiconductor]

Functional Overview
The Cypress CY7C65620/CY7C65630 USB 2.0 Hubs are high
performance, low system cost solutions for USB. The
CY7C65620/CY7C65630 USB 2.0 Hubs integrate 1.5 K
upstream pull-up resistors for full speed operation and all
downstream 15 K pull-down resistors and series termination
resistors on all upstream and downstream D+ and D– pins. This
results in optimization of system costs by providing built-in
support for the USB 2.0 specification.
System Initialization
On power-up, the CY7C65620/CY7C65630 reads an external
SPI EEPROM for configuration information. At the most basic
level, this EEPROM has the vendor ID (VID), product ID (PID),
and device ID (DID) for the customer’s application. For more
specialized applications, other configuration options can be
specified. See
details.
After reading the EEPROM, if VBUSPOWER (connected to
up-stream V
pull-up resistor on D+ to indicate its presence to the upstream
hub, after which a USB bus reset is expected. During this reset,
CY7C65620/CY7C65630 initiates a chirp to indicate that it is a
high-speed peripheral. In a USB 2.0 system, the upstream hub
responds with a chirp sequence, and CY7C65620/CY7C65630
is in a high speed mode, with the upstream D+ pull up resistor
turned off. In USB 1.x systems, no such chirp sequence from the
upstream hub is seen, and CY7C65620/CY7C65630 operates
as a normal 1.x hub (operating at full speed).
Enumeration
After a USB bus reset, CY7C65620/CY7C65630 is in an
unaddressed, unconfigured state (configuration value set to ’0’).
During the enumeration process, the host sets the hub's address
and configuration. After the hub is configured, the full hub
functionality is available.
Downstream Ports
The CY7C65620/CY7C65630 supports a maximum of four
downstream ports, each of which may be marked as usable or
removable in the extended configuration (0xD2 EEPROM load
or 0xD4 EEPROM load, see
Downstream D+ and D– pull-down resistors are incorporated in
CY7C65620/CY7C65630 for each port. Before the hubs are
configured, the ports are driven SE0 (single ended zero, where
both D+ and D– are driven low) and are set to the unpowered
state. When the hub is configured, the ports are not driven and
the host may power the ports by sending a SetPortPower
command for each port. After a port is powered, any connect or
disconnect event is detected by the hub. Any change in the port
state is reported by the hubs back to the host through the status
change endpoint (endpoint 1). On receipt of SetPortReset
Document Number: 38-08037 Rev. *T
BUS
) is high, CY7C65620/CY7C65630 enables the
Configuration Options on page 14
Configuration Options on page
for more
14.
request for a port with a device connected, the hub does as
follows:
■
■
■
■
Babble consists of a non-idle condition on the port after EOF2. If
babble is detected on an enabled port, that port is disabled. A
ClearPortEnable request from the host also disables the
specified port.
Downstream ports can be individually suspended by the host
with the SetPortSuspend request. If the hub is not suspended, a
remote wakeup event on that port is reflected to the host through
a port change indication in the hub status change endpoint. If the
hub is suspended, a remote wakeup event on this port is
forwarded to the host. The host may resume the port by sending
a ClearPortSuspend command.
Upstream Port
The upstream port includes the transmitter and the receiver state
machine. The transmitter and receiver operate in high-speed
and full-speed depending on the current hub configuration.
The transmitter state machine monitors the upstream facing port
while the hub repeater has connectivity in the upstream direction.
This machine prevents babble and disconnect events on the
downstream facing ports of this hub from propagating and
causing the hub to be disabled or disconnected by the hub to
which it is attached.
Power Switching
The CY7C65620/CY7C65630 includes interface signals for
external port power switches. Both ganged and individual
(per-port) configurations are supported, with individual switching
being the default. Initially all ports are unpowered. After
enumerating, the host may power each port by sending a
SetPortPower request for that port. The power switching and
overcurrent detection of downstream ports is managed by
control pins connected to an external power switch device. PWR
[n]# output pins of the CY7C65620/CY7C65630 series are
connected to the respective external power switch's port power
enable signals. Note that each port power output pin of the
external power switch must be bypassed with an electrolytic or
tantalum capacitor as required by the USB specification. These
capacitors supply the inrush currents, which occur during
downstream device hot-attach events. The polarity of this pin is
configured through the EEPROM; see
page
Overcurrent Detection
Overcurrent detection includes 8 ms of timed filtering by default.
This parameter is configured from the external EEPROM in a
range of 0 ms to 15 ms for both enabled ports and disabled ports
individually. Detection of overcurrent on downstream ports is
managed by control pins connected to an external power switch
device.
The OVR[n]# pins of the CY7C65620/CY7C65630 series are
connected to the respective external power switch’s port
Performs a USB reset on the corresponding port
Puts the port in an enabled state
Enables the green port indicator for that port (if not previously
overridden by the host)
Enables babble detection after the port is enabled.
14.
CY7C65620/CY7C65630
Configuration Options on
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