CY7C65632 CYPRESS [Cypress Semiconductor], CY7C65632 Datasheet
CY7C65632
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CY7C65632 Summary of contents
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... Internal regulator – single power supply 5 V required ❐ Provision of connecting 3.3 V with external regulator ❐ Integrated upstream pull-up resistor ❐ Integrated pull-down resistors for all downstream ports ❐ Integrated upstream/downstream termination resistors Block Diagram – CY7C65632 D+ D- 12/27/48 USB 2.0 PHY MHz OSC-in PLL OR 12 ...
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... Port Control ................................................................. 3 Applications ...................................................................... 3 Functional Overview ........................................................ 4 System Initialization ..................................................... 4 Upstream Port ............................................................. 4 Downstream Ports ....................................................... 4 Power Switching .......................................................... 4 Pin Configuration CY7C65632 – 48 TQFP ...................... 6 Pin Description for 48-Pin Package ................................ 8 Pin Description for 28-Pin Package .............................. 10 EEPROM Configuration Options ................................... 11 Pin Configuration Options ............................................. 12 Power-on Reset ......................................................... 12 Gang/Individual Power Switching Mode .................... 12 Document Number: 001-67568 Rev. *A PRELIMINARY Features Supported in 48-pin and 28-pin Packages ...
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... USB hub system. The CY7C65632 is a part of the HX2VL portfolio. This device option is for ultra low power but high performance applications that require up to four downstream ports. All downstream ports share a single transaction translator ...
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... CY7C65632 enables the pull-up resistor BUS indicate its presence to the upstream hub, after which a USB Bus Reset is expected. After a USB Bus Reset, CY7C65632 unaddressed, unconfigured state (configuration value set to ’0’). During the enumeration process, the host sets the hub's address and configuration ...
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... HX2VL. Configuring Port #1 and #2 as non-removable by pin-strapping should be avoided. Power Regulator CY7C65632 requires 3.3 V source power for normal operation of internal core logic and USB physical layer (PHY). The integrated low-drop power regulator converts 5 V power input from USB cable (Vbus) to 3.3 V source power. The 3.3 V power output is guaranteed by an internal voltage reference circuit when the input voltage is within the 5.5 V range. The regulator’ ...
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... Pin Configuration CY7C65632 – 48 TQFP 1 VCC_A 2 GND DD-[1] 6 DD+[1] 7 VCC_A 8 GND 9 DD-[2] 10 DD+[2] 11 RREF 12 VCC_A Document Number: 001-67568 Rev. *A PRELIMINARY CY7C65632 48 TQFP CY7C65632 AMBER[2] / SPI_DI / 36 PWR_PIN_POL GREEN[ SPI_DO / FIXED_PORT2 34 VCC_D AMBER[ SET_PORT_NUM2 GREEN[ FIXED_PORT3 31 PWR#[3] 30 OVR#[3] 29 PWR#[4] 28 OVR#[4] ...
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... Pin Configuration CY7C65632 – 28 QFN [ [1] VCC [ [2] 7 Document Number: 001-67568 Rev. *A PRELIMINARY CY7C65632 16 28 QFN 15 CY7C65632 VCC D _ OVR # [3] OVR # [4] TEST/SCL RESET [ [4] Page [+] Feedback ...
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... I2C_SCL: Can be used as I2C clock pin to access I2C EEPROM DN ) Upstream D– Signal. Upstream D+ Signal. Downstream D– Signal. Downstream D+ Signal. ) LED. Driver output for Amber LED. Port Indicator Support. Default is Active LOW. DN SPI_CS. Can be used as chip select to access external SPI EEPROM CY7C65632 = Pad internal UP Description Page [+] Feedback ...
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... LED. Driver output for Green LED. Port Indicator Support. Default is Active LOW. DN FIXED_PORT4. At POR used to set Port4 as non removable port. Refer configuration ) Section Overcurrent Condition Detection Input. Default is Active LOW. UP Power Switch Driver Output. Default is Active LOW. CY7C65632 = Pad internal UP Description Page [+] Feedback ...
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... Overcurrent Condition Detection Input. Default is Active LOW. GND in 2 port parts. Downstream D– Signal. Downstream D+ Signal. ) Overcurrent Condition Detection Input. Default is Active LOW. GND in 2 port parts. Ground pin for the chip the solderable exposed pad beneath the chip. Refer 2 on page 17. CY7C65632 = Pad internal UP Figure Page [+] Feedback ...
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... HX2VL can only read from SPI EEPROM. So, field programming of EEPROM is supported only for I2C EEPROM. CY7C65632 verifies the check sum after power on reset and if validated loads the configuration from the EEPROM. To prevent this configuration from being overwritten, amber LED is disabled Document Number: 001-67568 Rev ...
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... The individual or gang mode is decided within 20 us after power on reset. 50ms after reset, this pin is changed to output mode. CY7C65632 outputs the suspend flag, after it is globally suspended. Pull-down resistor of greater than 100 K is needed for Individual mode and a pull-up resistor greater than 100 K is needed for Gang mode ...
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... BOM cost by eliminating the external crystal. This is available through GPIO pin configuration shown as follows. This is not supported in the 28-QFN package SEL48 SEL27 CY7C65632 Clock Source 48 MHz OSC-in 27 MHz OSC-in 12 MHz X’tal/OSC-in Page [+] Feedback ...
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... High Speed Host, High Speed Devices High Speed Host, Full Speed Devices Full Speed Host, Full Speed Devices High Speed Host, High Speed Devices High Speed Host, Full Speed Devices Full Speed Host High Speed Host CY7C65632 Min Typ Max Unit 366.5 426.5 ...
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... DH t Clock to Output AA Document Number: 001-67568 Rev. *A PRELIMINARY SPI. The 28-pin QFN package can support Min Typ Max Units 3.0 3.0 1.0 2.2 us 1.8 2.4 1.8 1.8 1.8V - 5.5V 2.5V - 5.5V Min Max Min Max 0.0 100 0.0 400 4.7 - 1.2 - 4.0 - 0.6 - 4.7 - 0.6 - 4.7 - 0.6 - 4.0 - 0.6 - 4.0 - 0.6 - 200.0 - 100 100 - 50 - 0.1 4.5 0.1 0.9 CY7C65632 Units KHz Page [+] Feedback ...
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... GPIOs and EEPROM) XXX C Temperature grades: Commercial Package type: AX: TQFP (Pb-free) LTX: QFN (Pb-free) Pin count pins pins Specific product identifier Base part number Marketing code: 7C Company ID Cypress CY7C65632 Package Type 48-Pin TQFP Bulk 28-Pin QFN Bulk Page [+] Feedback ...
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... Package Diagrams The CY7C65632 is available in following packages: TOP VIEW NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED PAD 2. BASED ON REF JEDEC # MO-220 3. PACKAGE WEIGHT: ~0.05gr 4. DIMENSIONS ARE IN MILLIMETERS Document Number: 001-67568 Rev. *A PRELIMINARY Figure 1. 48-Pin TQFP Package Diagram Figure 2. 28-Pin QFN Package Diagram SIDE VIEW ...
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... IPOR imprecise power on reset Symbol μW microwatts mA milliampere ms millisecond mV millivolts nA nanoampere ns nanosecond nV nanovolts Ω ohm pA picoampere pF picofarad pp peak-to-peak ppm parts per million ps picosecond sps samples per second s sigma: one standard deviation V volts CY7C65632 Description Unit of Measure Page [+] Feedback ...
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... Document History Page Document Title: CY7C65632 HX2VL™ Very Low Power USB 2.0 Hub Controller Document Number: 001-67568 Orig. of Submission Revision ECN Change ** 3183649 SSJO/ 03/02/2011 New datasheet SWAK *A 3250883 SWAK/AASI 06/30/2011 1. In page 6, the pin of the 48-pin TQFP package was named SELF_PWR Document Number: 001-67568 Rev ...
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... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-67568 Rev. *A All products and company names mentioned in this document may be the trademarks of their respective holders. PRELIMINARY cypress.com/go/plc Revised June 30, 2011 CY7C65632 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...