CY2071ASXL-XXX CYPRESS [Cypress Semiconductor], CY2071ASXL-XXX Datasheet - Page 6

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CY2071ASXL-XXX

Manufacturer Part Number
CY2071ASXL-XXX
Description
Single-PLL General-Purpose EPROM Programmable Clock Generator
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Document #: 38-07139 Rev. *D
Switching Characteristics, Industrial 3.3V
Switching Waveforms
Test Circuit
Parameter
t
t
t
t
t
t
t
1
1A
1B
1C
3
4
5
OUTPUT
OUTPUT
OUTPUT
Output Period
Clock Jitter
Clock Jitter
Clock Jitter
Output Duty Cycle
Output Duty Cy-
cle
Rise time
Fall time
Skew
[12]
Name
[12]
[12]
[12]
V
DD
t
0.4V
3
t
2.4V
5
Clock output range 3.3V operation
15-pF load
Peak-to-peak period jitter (t
% of clock period, f
Peak-to-peak period jitter
(16 MHz ≤ f
Peak-to-peak period jitter (f
Duty cycle
f
Duty cycle
Output clock rise time
Output clock fall time
Skew delay between any two outputs with identi-
cal frequencies (generated by the PLL)
OUT
Figure 1. All Outputs Duty Cycle and Rise/Fall Time
0.1 µF
≤ 60 MHz
[13, 14]
[14]
Figure 2. Output-Output Clock Skew
t
OUT
2
for outputs, (t
≤ 50 MHz)
for outputs, (t
Description
OUT
[11]
7
OUTPUTS
t
2.4V
≤ 16 MHz
1
0.4V
GND
t
1
OUT
2
4
2
max. – t
÷ t
2
1
> 50 MHz)
÷ t
), f
1
CY2071AI
CY2071AFI
OUT
)
1
min.),
> 60 MHz
[66.6 MHz]
[80 MHz]
C
12.50
45%
40%
CLK output
Min.
15.0
LOAD
Typ.
50%
50%
350
250
0.8
1.5
1.5
[500 kHz]
[500 kHz]
V
0V
CY2071A
DD
Max.
2000
2000
55%
60%
500
350
2.5
2.5
0.5
1
Page 6 of 9
Unit
ns
ns
ps
ps
ns
ns
ns
%
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