DS152 XILINX [Xilinx, Inc], DS152 Datasheet - Page 56

• Manufacturer Part Number: DS152
• Description: Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
• Manufacturer: XILINX [Xilinx, Inc]

Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS152 (v2.10) October18, 2010
Advance Product Specification
01/18/10
02/09/10
04/12/10
05/11/10
05/26/10
07/16/10
07/23/10
07/30/10
09/20/10
10/18/10
Date
Version
2.10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Changed absolute maximum ratings for both V
data to
endurance
updated tables in the
Added
Added data to
and
specification changes and numerous updates also made to
Added data to
Revised description of C
Table
Added note 3 and update value of n in
Supply
Specifications. Updated speed specification to v1.05 with appropriate changes to
Table 43
Table
Table
Updated F
Clock CLK to ECCPARITY in standard ECC mode row in
Table
Added XC6VLX195T data to
Updated speed specification to v1.06 with appropriate changes to
production release of the XC6VLX195T for -1 and -2 speed grades. Added XC6VLX195T values to
Table
Changed
XC6VLX195T, and XC6VLX240T devices. Added XC6VHX250Tdata to
Note 6 to
Changed
XC6VLX760, XC6VSX315T, and XC6VSX475T devices using ISE 12.2 software with speed
specification v1.08. Updated V
some -3, -2, -1 specifications in
Table 41
Changed
XC6VLX195T, XC6VLX240T, XC6VLX365T, and XC6VLX550T devices using ISE 12.2 software with
current speed specifications. Also updated the speed specifications for XC6VLX75T, XC6VLX550T,
and XC6VSX315T. Updated V
devices in
In
F
The specification change in version 2.9,
Transceiver User Guide, Family Data Sheet (SYSMON DCLK), and JTAG ID Changes
In this version (2.10), -1L(I) data is added to
Table 43
XC6VSX475T devices using ISE 12.3 software with current speed specifications. Revised the
XC6VLX760 -1L speed specification for T
MAX
Table
Table 43
41.
47. Increased the -2 specification for F
52. Added note 1 to
71.
71.
for the DCLK from 250 MHz to 80 MHz.
Table 27
Table
Requirements. Updated external reference junction temperatures in
32, changed F
including production release of the XC6VLX130T for -1 and -2 speed grades. Fixed note 4 in
and for most switching characteristics tables.
to production status on the -1L speed grade XC6VLX75T, XC6VLX760, XC6VSX315T, and
Table 42
Table 42
Table
Table 42
RXREC
Table
Table
5. Updated SSTL15 in
including production release of the XC6VLX240T for -1 and -2 speed grades. Speed
Table
Table 72
63.
and
2.
12. Added values to V
in
and
and
and
Table
Figure
41. Updated speed specification to v1.04 with appropriate changes to
GTX Transceiver Specifications
Table 43
GPLLMAX
Table 43
Table 43
and
IN
22. Revised F
www.xilinx.com
Table
in
4. Revised parameters and values in
Table
Table
Table
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
CCINT
CMOUTDC
to production status on the XC6VLX75T, XC6VLX365T, XC6VLX550T,
Table 64
specification in -3 column from 5.951 to 5.591. In
61.
to production status on the -3 speed grade XC6VLX130T,
to production status on the -1L speed grade for the XC6VLX130T,
73.
5. Updated values in
3. Clarified values in
Table
specifications for -1L speed grade industrial temperature range
Description of Revisions
Table
MGTREFCLK
IDELAYCTRL_REF
Table 40
equation to MGTAVTT – D
through
PHMMCMGC
7. Updated V
3. Clarified simultaneous power-down in
IDELAYCTRL_REF
Table 4
IN
and V
Table
is described in XCN10032, Virtex-6 FPGA: GTX
and V
and clarified in Note 2. Changed
in
and
OCM
TS
71. Added and updated -1L specifications to
Table 68
in
Table
Table 22
IN
Table
in
GTH Transceiver Specifications
Table
and V
in
Table
Table
and clarified units for T
Table 13, page
5. Fixed SDR LVDS unit error in
56. Added XC6VLX130T values to
Table
52. Removed T
and T
OD
including adding note 2 and note 3.
44, and
1. Added data to
Table 42
VPPOUT
values in
39. Updated
PHMMCMCC
Table 4
Table 48
/4 in
Table
and
9. Added values and
Table
Table
and
RCKO_PARITY_ECC
Table 43
40,
Table 42
Table
in
Table 40, page
through
IDELAYPAT_JIT
Table
8. Added eFUSE
Power-On Power
Analog-to-Digital
Table
Table
17. Updated
Table 42
40, changed
including
3. Added
71. Added
sections.
69.
Table 42
and
Table
and
in
:
70.
21.
56