AD7357_08 AD [Analog Devices], AD7357_08 Datasheet - Page 16

• Manufacturer Part Number: AD7357_08
• Description: Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC
• Manufacturer: AD [Analog Devices]

AD7357
FULL POWER-DOWN MODE
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes
substantially longer than that from a partial power-down. This
mode is more suited to applications where a series of
conversions performed at a relatively high throughput rate are
followed by a long period of inactivity and thus, power-down.
When the AD7357 is in full power-down, all analog circuitry is
powered down. Full power-down is entered in a similar way as
partial power-down, except that the timing sequence shown in
Figure 25 must be executed twice. The conversion process must
be interrupted in a similar fashion by bringing CS high
anywhere after the second falling edge of SCLK and before the
D
D
D
D
D
D
SCLK
SCLK
OUT
SCLK
OUT
OUT
OUT
OUT
OUT
CS
CS
CS
A
B
A
B
A
B
THE PART BEGINS
TO POWER UP.
1
1
1
2
INVALID DATA
THE PART BEGINS
TO POWER UP.
PARTIAL POWER DOWN.
THE PART ENTERS
INVALID DATA
INVALID DATA
t
POWER-UP1
t
POWER-UP2
Figure 26. Exiting Partial Power-Down Mode
Figure 27. Entering Full Power-Down Mode
10
Figure 28. Exiting Full Power-Down Mode
10
THREE-STATE
10
Rev. PrF | Page 16 of 20
14
14
14
THE PART BEGINS
TO POWER UP.
10
mode at this point.
To reach full power-down, the next conversion cycle must be
interrupted in the same way, as shown in Figure 27. Once CS
has been brought high in this window of SCLKs, the part
completely powers down.
Note that it is not necessary to complete the 16 SCLKs once CS
has been brought high to enter a power-down mode.
To exit full power-down mode and power-up the AD7357,
perform a dummy conversion, such as powering up from partial
power-down. On the falling edge of CS , the device begins to
power up, as long as CS is held low until after the falling edge of
the 10
a conversion can be initiated, as shown in Figure 28.
th
falling edge of SCLK. The device enters partial power-down
1
th
SCLK. The required power-up time must elapse before
2
INVALID DATA
1
1
THE PART IS FULLY
POWERED UP; SEE
POWER-UP TIMES
SECTION.
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
FULL POWER DOWN.
THE PART ENTERS
Preliminary Technical Data
VALID DATA
VALID DATA
10
THREE-STATE
14
14
14