74LVCH16374A PHILIPS [NXP Semiconductors], 74LVCH16374A Datasheet - Page 2

• Manufacturer Part Number: 74LVCH16374A
• Description: 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs 3-State
• Manufacturer: PHILIPS [NXP Semiconductors]

1. C
Philips Semiconductors
FEATURES
DESCRIPTION
The 74LVC(H)16374A is a 16-bit edge-triggered flip-flop featuring
separate D-type inputs for each flip-flop and 3-State outputs for bus
oriented applications. The 74LVC16374A consists of 2 sections of
eight positive edge-triggered flip-flops. A clock (CP) input and an
output enable (OE) are provided for each octal. Inputs can be driven
from either 3.3V or 5V devices. In 3-State operation, outputs can
handle 5V. These features allow the use of these devices in a mixed
3.3V/5V environment.
The flip-flops will store the state of their individual D-inputs that meet
the set-up and hold time requirements on the LOW-to-HIGH CP
transition.
When OE is LOW, the contents of the flip-flops are available at the
outputs. When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the state of the
flip-flops.
The 74LVCH16374A bus hold data inputs eliminates the need for
external pull up resistors to hold unused inputs.
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
1998 Mar 17
5 volt tolerant inputs/outputs for interfacing with 5V logic
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
Low inductance multiple power and ground pins for minimum
noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16374A only)
High impedance when V
16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)
t
f
C
C
PHL
MAX
P
f
f
S (C
SYMBOL
i
o
I
PD
PD
D
= input frequency in MHz; C
= output frequency in MHz; V
= C
/t
L
PLH
is used to determine the dynamic power dissipation (P
PD
V
amb
PACKAGES
CC
TM
V
2
= 25 C; t
CC
flow-through standard pin-out architecture
Propagation delay
Cp to Qn
Maximum clock frequency
Input capacitance
Power dissipation capacitance per flip-flop
f
2
o
) = sum of outputs.
f
i
+ S (C
r
CC
= t
f
= 0
L
2.5 ns
L
PARAMETER
V
= output load capacity in pF;
CC
CC
= supply voltage in V;
2
TEMPERATURE RANGE
f
o
) where:
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
D
in mW):
C
V
V
CC
CC
L
OUTSIDE NORTH AMERICA
= 50pF
= 3.3V
= 3.3V
2
74LVCH16374A DGG
74LVC16374A DGG
74LVCH16374A DL
74LVC16374A DL
PIN CONFIGURATION
1
CONDITIONS
GND
GND
GND
GND
1OE
1Q4
1Q5
2Q3
2Q4
2Q6
2Q7
2OE
1Q0
1Q1
1Q2
1Q3
V
1Q6
1Q7
2Q0
2Q1
2Q2
V
2Q5
CC
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
NORTH AMERICA
VCH16374A DGG
VC16374A DGG
VCH16374A DL
VC16374A DL
SW00074
74LVCH16374A
74LVC16374A/
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TYPICAL
1CP
1D0
1D1
GND
1D2
1D3
V
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
V
2D4
2D5
GND
2D6
2D7
2CP
Product specification
CC
CC
150
3.8
5.0
30
DWG NUMBER
853-2028 19111
SOT370-1
SOT362-1
SOT370-1
SOT362-1
UNIT
MHz
pF
pF
ns