ISL54100 INTERSIL [Intersil Corporation], ISL54100 Datasheet
ISL54100
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ISL54100 Summary of contents
Page 1
... The receiver contains a programmable equalizer and a clock data recovery (CDR) function for each of the 3 TMDS pairs in an HDMI or DVI signal. The TMDS data outputs of the ISL54100 are regenerated and perfectly aligned to the regenerated TMDS clock signal, creating an extremely clean, low-jitter DVI/HDMI signal that can be easily decoded by any TMDS receiver ...
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... Block Diagram of ISL54100 2 RXC_A TERMINATION 2 RX0_A TERMINATION 2 RX1_A 2 EQUALIZATION RX2_A 2 RXC_B TERMINATION 2 RX0_B TERMINATION 2 RX1_B 2 EQUALIZATION RX2_B 2 RXC_C TERMINATION 2 RX0_C TERMINATION 2 RX1_C 2 EQUALIZATION RX2_C 2 RXC_D TERMINATION 2 RX0_D TERMINATION 2 RX1_D 2 EQUALIZATION RX2_D RES_TERM RES_BIAS GENERATION SDA SCL 7 ADDR PD RESET AUTO_CH_SEL CH_SEL_ 0 CH_SEL_1 ...
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... PU R Internal Pull-Down Resistance PD C Input Capacitance IN 3 ISL54100, ISL54101, ISL54102 ISL54100, ISL54101, ISL54102 Thermal Information Thermal Resistance (Typical, Note 1) +0.3V MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 D Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° ...
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... Operation up to 165MHz is guaranteed. While many parts will typically operate up to 225MHz, operation above 165MHz is not guaranteed SCL t SU:STA t HD:STA SDA IN SDA OUT 4 ISL54100, ISL54101, ISL54102 = 3.3V, pixel rate = 165MHz COMMENT All available inputs driven by 165Mpixel/s TMDS signals. Default register settings All available inputs driven by 165Mpixel/s TMDS signals ...
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... GND 24 GND RXC-_C 27 RXC+ RXC-_D 30 RXC+ GND RX0-_C 35 RX0+ RESET 38 ADDR3 5 ISL54100, ISL54101, ISL54102 CH_D_ACTIVE 102 101 CH_C_ACTIVE CH_B_ACTIVE 100 CH_A_ACTIVE GND 97 96 GND VD_ESD GND GND TXC TXC- 88 GND 87 TX2+ ...
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... RES_BIAS 23 GND 24 GND GND RESET 38 ADDR3 6 ISL54100, ISL54101, ISL54102 NC 102 NC 101 100 NC CH_A_ACTIVE GND 96 GND VD_ESD GND VD 92 GND 91 90 TXC+ 89 TXC- GND 88 87 TX2+ 86 TX2- ...
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... RES_BIAS 23 GND 24 GND GND RESET 38 ADDR3 7 ISL54100, ISL54101, ISL54102 102 NC NC 101 100 CH_B_ACTIVE CH_A_ACTIVE GND 97 GND 96 95 VD_ESD GND GND 90 TXC+ 89 TXC- 88 GND TX2 TX2- ...
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... TMDS Inputs. Incoming TMDS data signals for Channel D (ISL54100 only). RX2-_D, RX2+_D RXC-_A, RXC+_A, RXC-_B, RXC+_B, TMDS Inputs. Incoming TMDS clock signals for Channels and D (ISL54100), Channels A and B RXC-_C, RXC+_C, RXC-_D, RXC+_D (ISL54102), or Channel A (ISL54101). TX0-, TX0+, TX1-, TX1+, TX1-, TX1+ TMDS Outputs ...
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... Register Listing ADDRESS REGISTER (DEFAULT VALUE) 0x00 Device ID (read only) 0x01 Channel Activity Detect (read only) 0x02 Channel Selection (0x0C) 9 ISL54100, ISL54101, ISL54102 BIT(S) FUNCTION NAME 3:0 Device Revision 1 = initial silicon second revision, etc. 7:4 Device ISL5410x 0 Channel A Active 0: TMDS clock not present on Channel A ...
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... Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x03 Input Control (0x12) Recommended default: 0x62 10 ISL54100, ISL54101, ISL54102 BIT(S) FUNCTION NAME 0 Tri-state Unselected 0: Normal Operation Clock Inputs 1: Termination of unselected TMDS clock inputs is tri-stated to save power. Setting this bit will disable the activity detect function ...
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... REGISTER (DEFAULT VALUE) 0x04 Termination Control (0x00) 0x05 Output Options (0x00) 0x06 Data Output Drive (0x00) 11 ISL54100, ISL54101, ISL54102 BIT(S) FUNCTION NAME 0 Data Termination A 0: Channel A TMDS Data inputs terminated into 50Ω (normal operation) 1: Channel A TMDS Data inputs terminated into 100Ω (for ...
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... PRBS7 Error Counter Link 0 (read only) 0x0B PRBS7 Error Counter Link 1 (read only) 0x0C PRBS7 Error Counter Link 2 (read only) 0x10 PLL Bandwidth (0x10) Recommended default: 0x12 12 ISL54100, ISL54101, ISL54102 BIT(S) FUNCTION NAME 3:0 Channel A Equalizer Boost (dB) = 1dB + <gain value> * 0.8dB Gain 0x0: 1dB boost at 800MHz 7:4 Channel B Equalizer 0xC: 10 ...
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... Locked Loop (PLL). The PLL generates a low jitter pixel clock from the incoming TMDS clock. The TMDS data signals are equalized, sliced by the CDR, re-aligned to the PLL clock, and sent out the TMDS outputs. The ISL54100 and ISL54102 also include an input multiplexer. Multiplexer Operation The ISL54100 and ISL54102 have 4:1 and 2:1 (respectively) input multiplexers ...
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... TMDS termination resistors. This current is supplied by the ISL54100's V only 15 (0.5V*10mA per TMDS pair) is dissipated as power inside the ISL54100. The majority of the power (2.8V * 10mA per active TMDS pair) is dissipated in the TMDS transmitter driving the ISL54100. Likewise, the ISL54100 dissipates 85% of the power generated by the current from the external receiver attached to the ISL54100's Tx pins ...
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... VIDEO PATTERN GENERATOR 15m DUAL-LINK ISL54100 Given the input signal shown in Figure 6, the ISL54100’s TMDS output signal (Figure 8) is extremely clean. The output is an improvement over the original signal coming from the pattern generator in both amplitude and jitter. FIGURE 8. EYE DIAGRAM AT OUTPUT OF ISL54100 ...
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... Tx pins are high impedance. In this state they will draw no current from the Rx pins of any TMDS receiver they may be connected to. However if power to the ISL54100 is removed, the Tx pins are no longer high-impedance. Figure 10 shows the relevant equivalent circuit, including the internal ESD protection diodes ...
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... C BYPASS GROUND PLANE FIGURE 12. SUB-OPTIMAL BYPASS CAPACITOR LAYOUT 17 ISL54100, ISL54101, ISL54102 • Ideally each supply should be bypassed to ground with a 0.1µF capacitor. Minimize trace length and vias to minimize inductance and maximize noise rejection. Figure 12 demonstrates a common but non-ideal PCB layout and its equivalent circuit. The additional trace resistance between the bypass capacitor and the power supply/IC reduces its effectiveness ...
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... FROM TRANSMITTER DATA OUTPUT FROM RECEIVER FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER 18 ISL54100, ISL54101, ISL54102 transaction will be a Read (R Write (R/W = 0). If the address transmitted matches that of any device on the bus, that device must respond with an ACKNOWLEDGE (Figure 15). Once the serial address has been transmitted and acknowledged, one or more bytes of information can be written to or read from the slave ...
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... DATA STABLE Signals the beginning of serial I/O R/W ISL5410x Device Select Address Write The first 7 bits of the first byte select the ISL54100 on the 2-wire 0 ADDR1 ADDR0 bus at the address set by the ADDR[6:0} pins. The R/W bit indicating that the next transaction will be a write. ...
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... ISL54100, ISL54101, ISL54102 Signals the beginning of serial I/O R/W ISL5410x Device Select Address Write The first 7 bits of the first byte select the ISL54100 on the 2-wire 0 ADDR1 ADDR0 bus at the address set by the ADDR[6:0} pins. R indicating that the next transaction will be a write. ISL5410x Register Address Write ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 ISL54100, ISL54101, ISL54102 MDP0055 14x20mm 128 LEAD MQFP (WITH AND WITHOUT HEAT SPREADER) 3.2mm FOOTPRINT ...