LM9823CCWM NSC [National Semiconductor], LM9823CCWM Datasheet
LM9823CCWM
Available stocks
Related parts for LM9823CCWM
LM9823CCWM Summary of contents
Page 1
... V DGND CLMP SEN 12 17 VSMP 16 SDI 13 MCLK 15 14 SDO SCLK T +70°C A Device Marking 1 LM9823CCWM 2 LM9823CCWM 2 - Tape and reel transport media, 1000 parts per reel October 2000 16 Bits 6MHz 5V±5% 3.3V±10% or 5V±5% 375mW NS Package Number M28B M28B www.national.com ...
Page 2
Block Diagram 2 www.national.com ...
Page 3
... Coarse Color Balance PGA Characteristics Monotonicity G (Minimum PGA Gain (Maximum PGA Gain Boost Gain Gain Error at any gain (Note 13) Operating Ratings (Notes 1& 2) Operating Temperature Range 6.5V LM9823CCWM + -0. +0.3V V Supply Voltage A ±25mA V Supply Voltage D ±50mA (Note 4) OS ...
Page 4
Electrical Characteristics (Continued) The following specifications apply for AGND=DGND=0V, V for all other limits MIN MAX A Symbol Parameter Internal Reference Characteristics Mid Reference Output Voltage V REFMID Positive Reference ...
Page 5
DC and Logic Electrical Characteristics The following specifications apply for AGND=DGND=0V, V for all other limits MIN MAX A Symbol Parameter Power Supply Characteristics I Analog Supply Current A I Digital ...
Page 6
AC Electrical Characteristics Note 7: Two diodes clamp the OS analog inputs to AGND and V impedance of the sensor, prevents damage to the LM9823 from transients during power-up. Note 8: To guarantee accuracy required that V and ...
Page 7
Typical Performance Characteristics (Divide by 2, Monochrome Mode, 6 MHz Pixel Rate) Typical 16 Bit DNL 2 1.5 1 0.5 LSBs 0 -0 16384 32768 Output Code Typical 12 Bit DNL 1 0.5 LSBs 0 -0 ...
Page 8
Pin Descriptions Analog Power V The two V pins are the analog supply pins They should be connected to a voltage source of +5V and bypassed to 0.1µF monolithic capacitor in parallel with a 10µF tantalum capacitor. These ...
Page 9
Timing Diagrams MCLK VSMP ADC Clock (internal) N-1 Sample Signal Level Sample Reference Level D7 - N-5 DOE (Register 0, Bit Diagram 1: Divide by 6 Color ...
Page 10
Timing Diagrams (continued MCLK VSMP ADC Clock (internal) N-1 Sample Signal Level Sample Reference Level D7 - N-4 DOE (Register 0, Bit Diagram 4: Divide by 8 Monochrome Mode Sample and Data ...
Page 11
Timing Diagrams (continued MCLK VSMP Sample Signal Sample Reference D3 -D0 Diagram 7: Programmable Reference Sample Timing OS MCLK VSMP CLMP N-1 Sample Signal N Sample Reference CDSREF = 00 Clamp On ...
Page 12
Timing Diagrams (continued) t SCLK SCLK SEN t t SSU SH SDI SDO XX MCLK t t VSU VH VSMP t t CSU CH CLMP DDO Diagram 13: MCLK, VSMP ...
Page 13
Table 1: Configuration Register Address Table Address (Binary I/O Mode N/A 0 ...
Page 14
Table 2: Configuration Register Parameters Note: Power-Up Default Register Settings are shown in Bold Italics Parameter (Address) B7 I/O Mode 0 ( DOE 0 D7-D0 are clocked out (change) on the falling edge of MCLK - Recommended setting ...
Page 15
Table 2: Configuration Register Parameters Note: Power-Up Default Register Settings are shown in Bold Italics Parameter (Address) Red, Green and Blue Offset DAC Settings (1, 2 & Offset Polarity 0 1 Offset Value B4(MSB (SIGN) ...
Page 16
Table 2: Configuration Register Parameters Note: Power-Up Default Register Settings are shown in Bold Italics Parameter (Address Color Mode Reserved Register 0 Reserved Register 1 Reserved Register 2 (Continued) Control ...
Page 17
Applications Information 1.0 Introduction The LM9823 is a high performance scanner Analog Font End (AFE) for image sensor processing systems designed to work with color CCD and CIS image sensors and provides a full 3 channel sampling, gain ...
Page 18
Applications Information (Continued) 5.0 Offset DAC The Offset DACs remove the DC offsets generated by the sensor and the LM9823’s analog signal chain (see section 5.1, Internal Offsets). The DAC value for each color (registers 1,2 and 3) should be ...
Page 19
Applications Information (Continued) the OS input, the maximum allowable droop, the number of pixels on the sensor, and the pixel conversion rate, f the minimum clamp capacitor value CLAMP MIN = -------- - dt dV leakage current (A) ...
Page 20
Applications Information (Continued) less than the initial error. If the LM9823 is operating in CDS mode and multiple lines are used to charge up the clamping capacitors after power-up, then a clamp capacitor value of 0.01µF should be significantly greater ...
Page 21
Applications Information (Continued) an inappropriate value when operating in the lower “divide by” modes. Valid CDSREF settings are: “Divide By” Mode Valid CDSREF /8 00,01,10,11 /6 00,01,10,11 /3 00,01 /2 9.7 PD (Power Down) Mode A Power Down bit is ...
Page 22
... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Order Number LM9823CCWM NS Package Number M28B 2. A critical component is any component of a life support device ...