LM9823CCWM NSC [National Semiconductor], LM9823CCWM Datasheet - Page 6

• Manufacturer Part Number: LM9823CCWM
• Description: LM9823 3 Channel 48-Bit Color Scanner Analog Front End
• Manufacturer: NSC [National Semiconductor]

Note 7: Two diodes clamp the OS analog inputs to AGND and V
impedance of the sensor, prevents damage to the LM9823 from transients during power-up.
Note 8: To guarantee accuracy, it is required that V
both V
Note 9: Typicals are at T
Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11: Full channel integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer
function of the AFE.
Note 12: The sensor’s maximum peak differential signal range is defined as the peak sensor output voltage for a white (full scale) image, with respect to the dark reference
level.
Note 13:
Note 14: Full Channel INL and DNL are tested with CDS disabled, negative signal polarity, DOE = 0, and a single OS input with a gain register setting of 1 (000001b) and
an offset register setting of 0 (000000b).
Note 15: The digital supply current (I
The current required to switch the digital data bus can be calculated from: I
each data bit switching, C
is 8, P
example, if the capacitive load on each digital output pin (D7 - D0) is 20pF and the period of t
The calculated digital switching current will be drawn through the V
Note 16: All specifications quoted in LSBs are based on 12 bit resolution.
AC Electrical Characteristics
Gain
PGA
A
SW
and V
is
V
--- -
V
PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula
D
0.5, and V
=
are operated at 5.0V, they must be powered by the same regulator, with separate power planes or traces and separate bypass capacitors at each supply pin.
G
0
+
X
D
PGA code
-------------------------- -
J
L
=T
is 5V, and the switching current can be calculated from: I
is the capacitive loading on each data pin, V
32
A
=25°C, f
V
RFT
where
D
MCLK
) does not include the load, data and switching frequency dependent current required to drive the digital output bus on pins (D7 - D0).
V
REF
CCD Output Signal
= 12MHz, and represent most likely parametric norm.
X
=
G
31
A
V
and V
WHITE
–
G
0
D
32
----- -
31
be connected to clean, low noise power supplies, with separate bypass capacitors at each supply pin. When
(Continued)
.
OS Input
A
D
as shown below. This input protection, in combination with the external clamp capacitor and the output
pin and should be considered as part of the total power budget for the LM9823.
D
is the digital supply voltage and t
SW
= 2*N
AGND
V
Black Level
A
SW
6
D
*P
= 40*C
SW
*C
TO INTERNAL
CIRCUITRY
MCLK
L
L
/t
*V
MCLK
D
/t
is 1/12MHz or 83ns, then the digital switching current would be 9.6mA.
MCLK
. (With V
where N
MCLK
CIS Output Signal
D
is the period of the MCLK input. For most applications, N
at 3.3V, the equation becomes: I
D
is total number of data pins, P
V
WHITE
SW
SW
www.national.com
= 26.4*C
is the probability of
L
/t
MCLK
.) For
D