MAX5174AEEE MAXIM [Maxim Integrated Products], MAX5174AEEE Datasheet - Page 11

• Manufacturer Part Number: MAX5174AEEE
• Description: Low-Power, Serial, 12-Bit DACs with Voltage Output
• Manufacturer: MAXIM [Maxim Integrated Products]

Figure 2. Connections for SPI and QSPI Standards
Figure 3. Connections for MICROWIRE
Table 1. Serial-Interface Programming Commands
C1
0
0
1
1
1
1
1
1
1
MAX5174
MAX5176
MAX5174
MAX5176
16-BIT SERIAL WORD
C0
0
1
0
1
1
1
1
1
1
SCLK
SCLK
DIN
______________________________________________________________________________________
CS
DIN
CS
D11..................D0
1 0 0 x xxxx xxxx
1 0 1 x xxxx xxxx
1 1 0 x xxxx xxxx
1 1 1 x xxxx xxxx
0 0 x x xxxx xxxx
0 1 x x xxxx xxxx
12-bit DAC data
12-bit DAC data
xxxxxxxxxxxx
CPOL = 0, CPHA = 0
SK
SO
MOSI
SCK
I/O
I/O
MICROWIRE
Low-Power, Serial, 12-Bit DACs
SPI/QSPI
PORT
PORT
+5V
SS
S1, S0
0 0
0 0
xx
xx
xx
xx
xx
xx
xx
Load input register; DAC registers are unchanged.
Load input register; DAC registers are updated (start-up DAC with
new data).
Update DAC register from input register (start-up DAC with data
previously stored in the input registers).
No operation (NOP).
Shut down DAC (provided PDL = 1).
UPO goes low (default).
UPO goes high.
Mode 1, DOUT clocked out on SCLK’s rising edge.
Mode 0, DOUT clocked out on SCLK’s falling edge (default).
The MAX5174/MAX5176 accepts one 16-bit packet or
two 8-bit packets sent while CS remains low. The
MAX5174/MAX5176 allow the following to be config-
ured:
• Clock edge on which serial data output (DOUT) is
• State of the user-programmable logic output.
• Configuration of the reset state.
Specific commands for setting these are shown in
Table 1.
The general timing diagram in Figure 4 illustrates how
the MAX5174/MAX5176 acquires data. CS must go low
at least t
(SCLK). With CS low, data is clocked into the register
on the rising edge of SCLK. The maximum serial clock
frequency guaranteed for proper operation is 10MHz
for the MAX5174 and 6MHz for the MAX5176. See
Figure 5 for a detailed timing diagram of the serial inter-
face.
The serial-data output (DOUT) is the internal shift regis-
ter’s output and allows for daisy-chaining of multiple
devices as well as data readback (see Applications
Information ). By default upon start-up, data shifts out of
DOUT on the serial clock’s rising edge (Mode 0) and
provides a lag of 16 clock cycles, thus maintaining SPI,
QSPI, and MICROWIRE compatibility. However, if the
device is programmed for Mode 1, then the output data
lags DIN by 16.5 clock cycles and is clocked out on the
serial clock’s rising edge. During shutdown, DOUT
retains its last digital state prior to shutdown.
clocked.
with Voltage Output
CSS
before the rising edge of the serial clock
FUNCTION
Serial Data Output (DOUT)
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