MAX5316 MAXIM [Maxim Integrated Products], MAX5316 Datasheet - Page 22

• Manufacturer Part Number: MAX5316
• Manufacturer: MAXIM [Maxim Integrated Products]

The device is reset upon power-on, hardware reset using
RST, or software reset using register 0x4, bit 15, com-
mand RSTSW. After reset, the value of the input register,
the DAC latch and the output voltage are set to the values
defined by the M/Z input. If a hardware reset occurs dur-
ing a SPI programming frame, anything before and after
the reset for the frame will be ignored. A software reset
initiated through the SPI interface takes effect after the
end of the valid frame.
The output voltage can be set to either zero or mid-
scale upon power-up, or a hardware or software reset,
depending on the state of the M/Z input. After power-up,
if the device detects that this input is low, the output volt-
age is set to zero scale. If M/Z is high, the output voltage
is set to midscale.
Note that during reset, when RST is low or RSTSW is set
to 0, the output voltage is set slightly lower than the value
after coming out of reset. During reset, the output voltage
is set to the values shown for the V
tion in the Electrical Characteristics.
The device can be powered down by either hardware
(pulling PD high) or software (setting the PD_SW bit in
either the 0x4 or 0xC registers). Note that the hardware
and software inputs are ORed. Asserting either is enough
to place the device in power-down mode.
In order to restore normal operation to the device, satisfy
both of these conditions:
1) Pull PD low.
2) Set the bits PD_SW’s (in both 0x4 and 0xC registers)
In power-down, the output is internally connected to
AGND through a 2kI resistor. The SPI interface remains
active and the DAC register content remains unchanged.
The MAX5316 interprets the data code input (DIN) as
either straight binary or two’s complement. To choose the
straight binary format, set the TC/SB input low. For two’s
complement, set the input high.
to 0.
(Straight Binary vs. Two’s Complement)
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Output State Upon Reset
Data Format Selection
16-Bit, ±1 LSB Accuracy Voltage Output
OUT-RESET
Power-Down
specifica-
Reset
The BUSY line is open drain and is normally pulled up by
an external resistor. It is software-configurable to be bidi-
rectional and can be pulled down externally. Whenever
the DIN register is changed, the device transfers the
value to the DAC register. To indicate to the host proces-
sor that the device is busy transferring, the device pulls
the BUSY output low. Once transfer is complete, the
device releases BUSY and the host processor can load
the DAC by toggling the LDAC input. If LDAC is set low
while BUSY is low, the LDAC event is latched and imple-
mented when the transfer is complete and BUSY rises.
There are four ways in which the LDAC and BUSY out-
puts can be used. This is shown graphically in
1) The host sends a new command. The device sets
2) The host sends a new command. The device sets
3) LDAC is held low. The host sends a new command
4) BUSY is pulled down externally to delay DAC update.
If the DAC must be updated at a precise time with the
least amount of jitter, use option 1.
BUSY low. The host monitors BUSY to determine
when it goes high. The device then pulses LDAC low
to update the DAC.
BUSY low. The host toggles LDAC low then high
before BUSY goes high. The device latches the LDAC
event but does not implement it until processing is
complete. Then, BUSY goes high and the device
updates the DAC.
and the device sets BUSY low. The device updates
the DAC when the processing is complete and BUSY
goes high.
The BUSY pin is bidirectional. To use BUSY as an
input, set the NO_BUSY bit to 1 using the 0x4 or
0xC command. When configured as an input, pulling
BUSY low at least 50ns before the device releases
the line delays DAC update. DAC update occurs only
after BUSY is released and goes high. If used as an
input, drive BUSY with an open-drain output with a
pullup to V
DAC with SPI Interface
DDIO
.
LDAC and BUSY Interaction
MAX5316
Figure
4.