ADCS9888CVH-140 NSC [National Semiconductor], ADCS9888CVH-140 Datasheet - Page 24

• Manufacturer Part Number: ADCS9888CVH-140
• Description: 205/170/140 MSPS Video Analog Front End
• Manufacturer: NSC [National Semiconductor]

www.national.com
Application Information
In dual channel output modes, if Register 15H, Bit 5 is set to
one, then HSOUT will transition on the rising edge of
DATACK instead of the falling edge as shown in the timing
diagrams.
All DATA and DATACK outputs are placed in high impedance
tri-state mode when the chip is in power down. No pull-up or
pull-down features are present in the high impedance state.
Refer to the specific sections regarding the other logic out-
puts for their configuration during power down or low power
modes of chip operation.
2.6.1 Output Termination
All data and timing outputs are high speed CMOS drivers
and should be properly terminated to reduce EMI and opti-
mize signal integrity. Each output should have a series ter-
minating resistor located as close to the output pin as pos-
sible. The value of the terminating resistor is dependant on
3.0 SYNC INPUTS AND PROCESSING
3.1 SYNC On Green Input
The Sync-On-Green input is provided to support applications
where separate TTL Hsync and Vsync inputs are not pro-
vided. In these applications, the composite sync information
is provided on the Green video signal. The SOG input ac-
cepts an AC coupled version of the green input signal. This
signal is clamped, and then further processed to extract the
horizontal and vertical sync signals.
3.1.1 Sync Slicer
The Sync Slicer is an adjustable clamp/comparator. First the
input is clamped so that the most negative voltage is set to
equal an internal reference voltage. This clamped signal is
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24
the printed circuit board trace impedance. The optimum
performance will be when the output impedance of the chip
plus the terminating resistor is equal to the characteristic
impedance of the printed circuit board trace. Typical output
impedance of the ADCS9888 SOGOUT, DATACK and
DATACKB is around 30Ω, while the HSOUT, VSOUT and
DATA are 90Ω. So for a 150Ω trace impedance, the optimum
terminating resistor values would be 120Ω and 60Ω respec-
tively.
then fed into a 5 bit adjustable comparator to provide a logic
level signal with the analog video data removed and only the
sync signals remaining. The default comparator setting is
160 mV above the reference voltage. Adjustment increments
are in 10 mV intervals with a resulting comparator range
from 10 mV to 330 mV.
Optimal settings will be lower than those used with the
Analog Devices AD9888. The recommended starting value
is a setting of 01111b, but the best setting is dependent on
amplitude of the input video signal and synchronizing pulse.
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