ADCS9888CVH-140 NSC [National Semiconductor], ADCS9888CVH-140 Datasheet - Page 25

• Manufacturer Part Number: ADCS9888CVH-140
• Description: 205/170/140 MSPS Video Analog Front End
• Manufacturer: NSC [National Semiconductor]

Application Information
The Sync Slicer output has the same polarity as the input
signal. “Normal” video with white positive and black negative
will produce sync pulses that are active low. Normal synchro-
nization signals will be mainly high with pulses going low.
The Sync Slicer circuit will provide an active logic output
from many signals which do not have sync on green present.
Video with no Sync On Green signal present will still cause
the output of the Sync Slicer circuit to toggle. The timing of
this output will be much different than that caused by a signal
where Sync On Green information is included. In addition,
when no Sync On Green information is present, timing will
always be provided on the VSYNC and/or HSYNC timing
inputs.
3.1.2 Sync on Green Activity Detect
The SOGIN activity detect circuit detects the absence or
presence of a signal at the output of the Sync Slicer. The
result of this detection is sent to Register 14h, Bit 1. (1 =
Active, 0 = Inactive)
3.2 HSYNC Input
In most computer video applications, a TTL horizontal sync
pulse is output by the graphics card. This TTL signal is
connected to the ADCS9888 HSYNC input. In other applica-
tions a TTL composite sync signal may be used. To support
this, the composite sync signal from the HSYNC input can be
processed by the Sync Separator circuit to generate a Vsync
signal. Either Hsync signal (from HSYNC input or from SO-
GIN via the Sync Slicer) can be used as the reference clock
for the PLL in the clock generation block.
3.2.1 HSYNC Activity Detect
The HSYNC activity detect circuit detects the absence or
presence of an HSYNC input signal. The result of this de-
tection is sent to Register 14h, Bit 7. (1 = Active, 0 = Inactive)
3.2.2 AHS - Active HSYNC Selection
The Clock Generator will use either the HSYNC input, or the
output from the Sync Slicer as the reference for the PLL. The
AHS performs an automatic selection of the PLL reference
source based on the following table:
3.2.3 Hsync Polarity Detection
The Hsync signal input to the Clock Generator can be an
active high or active low signal. A polarity detection circuit is
used to detect the state of the Hsync signal. Signals that are
mostly low with pulses high will be reported as active high or
positive, while signals that are mostly high with pulses low
will be reported as active low or negative. The results of this
detection are reported in Register 14h, Bit 5. (0 = Negative,
1 = Positive).
Reg. 14h
Bit 7
Hsync
Detect
0
0
1
1
X
Reg. 14h
Bit 1
SOG
Detect
0
1
0
1
X
Reb. 0Eh
Bit 4
Override
0
0
0
0
1
0 – use HSYNC
1 – use SOG
0 – use HSYNC
0Eh, Bit 3
0Eh, Bit 3
(Continued)
AHS Output
25
Regardless of the polarity of the Hsync signal at the detector,
an automatic polarity correction circuit is used to ensure that
the proper polarity signal is used to drive the PLL reference
clock input.
3.3 SYNC Separator
Either the SOGIN or HSYNC signals can have a composite
sync signal as the input. MUX1 is used to feed this compos-
ite sync from either source into the sync separator. The sync
separator is a digital low pass filter that has an adjustable
number of clock ticks from 0 to 255. The default setting is 32
ticks. This filter rejects changes in the composite sync signal
that are shorter than the period set. Thus, only long duration
changes in the digital composite sync signal, i.e. the vertical
sync pulse, are allowed to pass through. The separator uses
an internal clock with a nominal frequency of 5 MHz as the
filter timebase.
3.4 VSYNC Input
The VSYNC input accepts a TTL vertical sync pulse pro-
vided by the video source. This signal or the vertical sync
signal output by the Sync Separator can be used to control
the Coast function in the clock generation circuitry.
3.4.1 Vsync Activity Detect
The Vsync activity detect circuit detects the absence or
presence of a Vsync input signal. The result of this detection
is sent to Register 14h, Bit 4. (1 = Active, 0 = Inactive).
3.4.2 Vsync Polarity Detect
The Vsync signal can be an active high or active low signal.
A polarity detection circuit is used to detect the active state.
The polarity is determined by observing the high/low duty
cycle of the VSOUT signal to determine whether the signal is
mostly high or mostly low. If the signal is mostly low, then the
polarity is set as Positive. If the signal is mostly high, then the
polarity is set to Negative. (0 = Negative, 1 = Positive) The
results of this detection are sent to Register 14h, Bit 2.
3.4.3 AVS - Active Vsync Detection
There are two possible signal sources for VSOUT. The
Vsync input can be used, or the output of the SYNC SEPA-
RATOR can be used. The AVS automatically selects the
source for VSOUT based on the results and settings de-
scribed in the following table.
4.0 CLOCK GENERATION
The PLL clock generator provides a high frequency pixel
clock that is phase aligned to the horizontal sync signal. The
horizontal sync signal can be provided by the HSYNC input,
or the output of the sync slicer circuit. The pixel clock is used
as the timing source for the analog to digital conversion and
data output processing in the IC.
Reg. 14h
Bit 4
Vsync
Detect
0
0
1
1
X
Reg. 14h
Bit 1
SOG
Detect
0
1
0
1
X
Reg. 0Eh
Bit 1
Override
0
0
0
0
1
Reg 0Eh, Bit 0
1 – use SOG
0 – use VSYNC
0 – use VSYNC
Reg 0Eh, Bit 0
AHS Output
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