AD9211-170EB AD [Analog Devices], AD9211-170EB Datasheet
AD9211-170EB
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AD9211-170EB Summary of contents
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... RESET SCLK SDIO CSB Figure 1. Functional Block Diagram Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead chip scale package (56 LFCSP) specified over the industrial temperature range (–40°C to +85°C). PRODUCT HIGHLIGHTS 1. High Performance—Maintains 60 dB SNR @ 250 MSPS with a 65 MHz input ...
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... Analog Input and Reference Overview ................................... 14 Clock Input Considerations ...................................................... 15 Preliminary Technical Data Power Dissipation and POWER DOWN Mode .................... 16 Digital Outputs ........................................................................... 17 Timing ......................................................................................... 17 RBIAS........................................................................................... 18 AD9211 Configuration Using the SPI ..................................... 18 Hardware Interface..................................................................... 19 Reading the Memory Map Table.............................................. 19 Open Locations .......................................................................... 19 Default Values ............................................................................. 19 Logic Levels................................................................................. 19 Outline Dimensions ....................................................................... 21 Ordering Guide ...
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... Internal Reference, MAX IN AD9211-250 Max Min Typ Max 10 Guaranteed TBD TBD ± 0.3 ± 0.3 ± 0.5 ± 0.5 TBD TBD 1.25 1 1.9 1.7 1.8 1.9 1.9 1.7 1.8 1.9 151 60 380 TBD AD9211 Unit Bits LSB LSB LSB LSB μV/°C %/° kΩ mV/V ...
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... Rev. PrA | Page Preliminary Technical Data AD9211-250 Min Typ Max 59.5 60 59.5 58.5 57.5 9.6 9.6 9.6 9.6 9.4 9.2 –80 –80 –80 –80 –77 –75 –85 –85 –85 –85 – ...
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... VDD .2 x AVDD 247 454 1.125 1.375 Twos Complement, or Binary Rev. PrA | Page AD9211-250 Min Typ Max tbd tbd tbd 4 2.0 0 247 454 1.125 1.375 Twos Complement, or Binary AD9211 Unit V V kΩ μA μ ...
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... TBD TBD TBD 3.9 0.4 0.4 3.2 TBD 5 TBD 0.2 TBD N+1 N+L L CYCLES 1 N–L N-L+1 Figure 2. Timing Diagram (L=5 Cycles) Rev. PrA | Page Preliminary Technical Data AD9211-250 Typ Max Unit MSPS 40 MSPS 3.9 ns 0.4 ns 0.4 ns 3.2 ns TBD ns 5 Cycles TBD ns 0.2 ps rms TBD Cycles N+L+2 ...
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... Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 1 Rev. PrA | Page AD9211 ...
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... DCO+ 51-54 DNC 55 D0– 56 D0+ 1 AGND and DRGND should be tied to a common quiet ground plane. 1 D1- 2 D1+ 3 D2- 4 D2+ 5 D3- 6 AD9211 D3 Lead for LF-CSP 8 TOP VIEW 9 D4- (Not to Scale) 10 D4+ 11 D5- 12 D5+ 13 D6- 14 D6+ Pin 0 (exposed paddle) = AGND Figure 3. Pinout Description 1 ...
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... D5 Complement Output Bit. D5 True Output Bit. D6 Complement Output Bit. D6 True Output Bit. D7 Complement Output Bit. D7 True Output Bit. D8 Complement Output Bit. D8 True Output Bit. D9 Complement Output Bit. D9 True Output Bit. Overrange Complement Output Bit. Overrange True Output Bit. Rev. PrA | Page AD9211 ...
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... AD9211 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the Clock and the instant at which the analog input is sampled. ...
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... Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Rev. PrA | Page AD9211 ...
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... AD9211 EQUIVALENT CIRCUITS AVDD AVDD AVDD Vcm CLK+ 10k 10k Figure 4 Clock Inputs AVDD VIN+ BUF 1000 Ω BUF 1000 Ω AVDD VIN- BUF Figure 5. Analog Inputs (VX=~ 1.3V) AVDD IN Figure 6. Logic Inputs AVDD CLK- . AVDD AVDD Rev. PrA | Page Preliminary Technical Data ...
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... Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS TBD Rev. PrA | Page AD9211 ...
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... Figure 8. Differential Input Configuration Using the AD8138 At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9211. This is especially true in IF under-sampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration ...
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... The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD9211 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9211 while preserving the fast rise and fall times of the signal, which are critical to a low jitter performance ...
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... POWER DISSIPATION AND POWER DOWN MODE As shown in Figure 12 and Figure 14, the power dissipated by the AD9211 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. ...
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... An additional stand by mode is supported by means of varying the clock input. When the clock rate falls below 20MHz, the AD9211 will assume a standby state. In this case, the biasing network and internal reference remain on but digital circuitry is powered down. Upon reactivating the clock, the AD9211 will resume normal operation after allowing for the pipeline latency ...
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... At clock rates below 1 MSPS, the AD9211 will assume standby mode. RBIAS The AD9211 requires the user to place a 10K Ω resistor between the RBIAS pin and ground. This resister should have a 1% tolerance, and is used to set the master current reference of the ADC core. ...
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... The pins described in Table X comprise the physical interface between the user’s programming device and the serial port of the AD9211. All serial pins are inputs, which is an open-drain output and should be tied to an external pull-up or pull-down resistor (suggested value 10 kΩ). ...
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... AD9211 Table X. AD9211 Device Configuration Register Memory Map . Preliminary Technical Data Rev. PrA | Page ...
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... AD9211BCPZ-250 −40°C to +85°C AD9211-250EB 25°C AD9211-200EB 25°C AD9211-170EB 25°C 1 Z=Pb-free part © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. PR06041-0-3/06(PrA) 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] ...