AD1839AASZ-REEL1 AD [Analog Devices], AD1839AASZ-REEL1 Datasheet
AD1839AASZ-REEL1
Related parts for AD1839AASZ-REEL1
AD1839AASZ-REEL1 Summary of contents
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FEATURES 5 V stereo audio system with 3.3 V tolerant digital interface Supports kHz sample rates 192 kHz sample rate available on 1 DAC Supports 16-/20-/24-bit word lengths Multibit Σ-∆ modulators with perfect differential linearity restoration for ...
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AD1839A TABLE OF CONTENTS Specifications..................................................................................... 3 Test Conditions............................................................................. 3 Timing Specifications....................................................................... 5 Absolute Maximum Ratings............................................................ 7 Temperature Range ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 Terminology .................................................................................... 11 Functional Overview...................................................................... 12 ...
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SPECIFICATIONS TEST CONDITIONS Supply Voltages 5.0 V (AVDD, DVDD) Ambient Temperature 25°C Input Clock 12.288 MHz (256 × f DAC Input Signal 1.0078125 kHz, 0 dBFS 1.0078125 kHz, −1 dBFS ADC Input Signal Input Sample Rate ( kHz ...
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AD1839A Parameter 1 ADC DECIMATION FILTER, 48 kHz Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay ADC DECIMATION FILTER, 96 kHz 1 Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 48 kHz 1 ...
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TIMING SPECIFICATIONS Table 2. Parameter MASTER CLOCK AND RESET PDR SPI PORT t CCH t CCL t CCP t CDS t CDH t CLS t CLH t COE t COD t COTS DAC SERIAL PORT ...
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AD1839A Parameter TDM256 MODE (Master, 48 kHz and 96 kHz) t TBD t FSD t TABDD t TDDS t TDDH TDM256 MODE (Slave, 48 kHz and 96 kHz TBCH t TBCL t TFS t TFH t TBDD ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Rating AVDD, DVDD, ODVDD to AGND, DGND −0 +6.0 V AGND to DGND −0 +0.3 V Digital I/O Voltage to DGND −0.3 V ...
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AD1839A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CONNECT Table 5. Pin Function Descriptions Pin No. Mnemonic 1, 39 DVDD 2 CLATCH 3 CIN 4 PD/RST 5, 10, 16, 24, 30, 34 AGND 6, 8, 12, 14, 25, 27, ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0 –50 –100 –150 FREQUENCY (Normalized to Figure 4. ADC Composite Filter Response 5 0 –5 –10 –15 –20 –25 – FREQUENCY (Hz) Figure 5. ADC High-Pass Filter Response ...
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AD1839A 0 –50 –100 –150 0 50 100 FREQUENCY (kHz) Figure 10. DAC Composite Filter Response, f 0.10 0.05 0 –0.05 –0. FREQUENCY (kHz) Figure 11. DAC Composite Filter Response kHz (Pass-Band Section) S ...
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TERMINOLOGY Dynamic Range The ratio of a full-scale input signal to the integrated input noise in the pass band ( kHz), expressed in decibels. Dynamic range is measured with a −60 dB input signal and is equal ...
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AD1839A FUNCTIONAL OVERVIEW ADCS There are two ADC channels in the AD1839A, configured as a stereo pair. Each ADC has fully differential inputs. The ADC section can operate at a sample rate kHz. The ADCs include ...
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To maintain the highest performance possible, the clock jitter of the master clock signal should be limited to less than 300 ps rms, measured using the edge-to-edge technique. Even at these levels, extra noise or tones may appear in the ...
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AD1839A SERIAL DATA PORTS—DATA FORMAT The ADC serial data output mode defaults to the popular I format, where the data is delayed by 1 BCLK interval from the edge of the LRCLK. By changing Bits ADC ...
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LRCLK LEFT CHANNEL BCLK SDATA MSB LEFT CHANNEL LRCLK BCLK MSB SDATA LEFT CHANNEL LRCLK BCLK MSB SDATA RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL LRCLK BCLK SDATA MSB NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL LRCLK ...
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AD1839A t DBH DBCLK t DBL t DLS DLRCLK t DSDATA DDS LEFT-JUSTIFIED MSB MODE t DDH DSDATA COMPATIBLE MODE DSDATA RIGHT-JUSTIFIED MODE LRCLK BCLK ADC DATA LRCLK BCLK ADC DATA MSB – DDS MSB ...
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LRCLK 128 BCLKs BCLK 16 BCLKs SLOT 1 SLOT 2 SLOT 3 SLOT 4 DAC DATA LEFT 1 LEFT 2 LEFT 3 LEFT 4 MSB MSB – 1 MSB – 2 Figure 21. DAC Packed Mode 128 LRCLK 256 BCLKs ...
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AD1839A FSTDM BCLK TDM MSB TDM ASDATA1 1ST CH TDM (OUT) INTERNAL ASDATA ADC L1 MSB TDM DSDATA1 1ST CH TDM (IN) INTERNAL DSDATA1 DAC L1 AUX 2 LRCLK I S (FROM AUX ADC NO. 1) AUX 2 BCLK I ...
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LRCLK BCLK ADC NO. 1 SLAVE DATA MCLK LRCLK BCLK ADC NO. 2 SLAVE DATA MCLK LRCLK BCLK ADC NO. 3 SLAVE DATA MCLK CONTROL/STATUS REGISTERS The AD1839A has 13 control registers which are used to set ...
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AD1839A ADC Control Registers The AD1839A register map has five registers that are used to control the functionality and read the status of the ADCs. The function of the bits in each of these registers is discussed below. ADC Peak ...
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Table 11. DAC Control 1 Address R/W RES De-emphasis 15, 14, 13 0000 None 01 = 44.1 kHz 10 = 32.0 kHz 11 = 48.0 kHz Table 12. DAC Control 2 ...
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AD1839A Table 16. ADC Control 2 R/W Address RES Master/Slave Aux Mode 15, 14, 13 1101 Slave 1 = Master Table 17. ADC Control 3 R/W RES Address RES Reserved 15, 14, ...
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AUX ADC (SLAVE) DRx ASDATA RFSx ALRCLK RCLKx ABCLK SHARC (SLAVE) TFSx TCLKx DTx TFSx/ RFSx DTx L1 L2 DRx L1 L2 BCLK MSB DTx MSB DRx 47µF 600Z 5.76kΩ 5.76kΩ AUDIO + INPUT 120pF NPO 100pF NPO 237Ω OP275 ...
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... AD1839AAS-REEL −40°C to +85°C 1 AD1839AASZ −40°C to +85°C 1 AD1839AASZ-REEL −40°C to +85°C EVAL-AD1839AEB −40°C to +85° Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...