ADC774JH BURR-BROWN [Burr-Brown Corporation], ADC774JH Datasheet - Page 6

• Manufacturer Part Number: ADC774JH
• Description: Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

Figure 1 illustrates timing when conversion is initiated by an
R/C pulse which goes low and returns to the high state
during the conversion. In this case, the three-state outputs
go to the high-impedance state in response to the falling
edge of R/C and are enabled for external access of the data
after completion of the conversion. Figure 2 illustrates the
timing when conversion is initiated by a positive R/C pulse.
In this mode the output data from the previous conversion is
enabled during the positive portion of R/C. A new conver-
sion is started on the falling edge of R/C, and the three-state
outputs return to the high-impedance state until the next
occurrence of a high R/C pulse. Timing specifications for
stand-alone operation are listed in Table III.
FIGURE 3. Conversion Cycle Timing.
TABLE IV. Timing Specifications.
DB11–
DB0
STS
R/C
CE
CS
A
Read Mode
O
SYMBOL
t
SAC
t
t
SSC
SRC
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DSC
HEC
HSC
SRC
HRC
HAC
t
HSR
HRR
HAR
t
SSC
SAC
SSR
SAR
t
DD
HD
HL
HS
C
®
ADC774
t
DSC
t
t
t
HSC
HRC
HAC
High Impedance
t
HEC
PARAMETER
STS Delay from CE
CE Pulse Width
CS to CE Setup time
CS low during CE high
R/C to CE setup
R/C low during CE high
A
A
Conversion time
Access time from CE
Data valid after CE low
Output float delay
CS to CE setup
R/C to CE setup
CS valid after CE low
R/C high after CE low
A
STS delay after data valid
O
O
O
to CE setup
valid during CE high
valid after CE low
12-bit cycle at 25 C
8-bit cycle at 25 C
t
C
0 to +75 C
–55 C to +125 C
0 to +75 C
–55 to +125 C
6
FULLY CONTROLLED OPERATION
Conversion Length
Conversion length (8-bit or 12-bit) is determined by the state
of the A
sion start transition (described below). If A
the conversion continues for 8 bits. The full 12-bit conver-
sion will occur if A
an 8-bit conversion, the 3 LSBs (DB0–DB2) will be low
(logic 0) and DB3 will be high (logic 1). A
because it is also involved in enabling the output buffers. No
other control inputs are latched.
FIGURE 4. Read Cycle Timing.
DB11–
DB0
STS
R/C
CE
CS
A
O
MIN
50
50
50
50
50
50
25
50
50
0
0
0
0
O
input, which is latched upon receipt of a conver-
t
t
t
SSR
SRR
SAR
O
TYP
100
150
7.5
60
30
20
20
20
20
75
35
0
5
0
is low. If all 12 bits are read following
High-Z
t
DD
t
HS
MAX
200
150
150
375
8.5
9.0
9.5
5.3
5.6
6
t
Data Valid
t
t
HSR
HRR
HAR
O
is latched high,
t
O
HL
UNITS
t
HD
is latched
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s