AD7228ABQ AD [Analog Devices], AD7228ABQ Datasheet - Page 3

• Manufacturer Part Number: AD7228ABQ
• Description: LC2MOS Octal 8-Bit DAC
• Manufacturer: AD [Analog Devices]

REV. A
+5 V SUPPLY OPERATION
Parameter
STATIC PERFORMANCE
REFERENCE INPUT
POWER REQUIREMENTS
NOTES
All of the specifications as per Dual Supply Specifications except for negative full-scale settling-time when V
Specifications subject to change without notice.
SWITCHING CHARACTERISTICS
NOTES
1
2
INTERFACE LOGIC INFORMATION
Address lines A0, A1 and A2 select which DAC accepts data
from the input port. Table I shows the selection table for the
eight DACs with Figure 1 showing the input control logic.
When the WR signal is low, the input latch of the selected DAC
is transparent, and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of WR. While WR is high, the analog outputs remain
at the value corresponding to the data held in their respective
latches.
AD7228A Control Inputs
WR
H
L
g
L
L
L
L
L
L
L
H = High State L = Low State X = Don’t Care
Sample tested at 25 C to ensure compliance. All input rise and fall times measured from 10% to 90% of +5 V, t
Timing measurement reference level is
Parameters
Resolution
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Zero Code Error
Reference Input Range
Reference Input Resistance
Reference Input Capacitance
Positive Supply Range
Positive Supply Current
Negative Supply Current
@ 25 C
T
@ 25 C
T
@ 25 C
T
t
t
t
t
t
MIN
MIN
MIN
1
2
3
4
5
to T
to T
to T
A2
X
L
L
L
L
L
H
H
H
H
MAX
MAX
MAX
Table I. AD7228A Truth Table
A1
X
L
L
L
H
H
L
L
H
H
Limit at 25 C
All Grades
70
10
95
0
0
A0
X
L
L
H
L
H
L
H
L
H
V
INH
2
B
Version
8
1.2
1.3
2
4.75/5.25
16
20
14
18
500
V
2
1
4
30
40
INL
(V
unless otherwise noted.) AII specifications T
DD
Limit at T
AD7228A
Operation
No Operation
Device Not Selected
DAC 1 Transparent
DAC 1 Latched
DAC 2 Transparent
DAC 3 Transparent
DAC 4 Transparent
DAC 5 Transparent
DAC 6 Transparent
DAC 7 Transparent
DAC 8 Transparent
= +5 V
(B, C Versions)
1, 2
C
Version
8
1.2
1.3
2
500
4.75/5.25
16
20
14
18
120
2
1
2
20
30
90
10
0
0
MIN
(See Figures 1, 2; V
5%, V
, T
MAX
SS
; = 0 to –5 V
T
Version
8
1.2
1.3
2
500
4.75/5.25
16
22
14
20
–3–
2
1
4
30
40
Limit at T
DD
(T, U Versions)
= +5 V
SS
10%, GND = 0 V, V
100
150
10
= 0 V.
0
0
MIN
R
= t
U
Version
8
1.2
1.3
2
500
4.75/5.25
16
22
14
20
Figure 2. Write Cycle Timing Diagram
, T
2
1
2
20
30
MIN
F
= 5 ns.
5% or +10.8 V to +16.5 V; V
MAX
to T
Figure 1. Input Control Logic
MAX
unless otherwise noted.
REF
ns min
ns min
Units
ns min
ns min
ns min
Units
Bits
LSB max
LSB max
LSB max
mV max
mV max
V min
V max
k min
pF max
V min/V max
= +1.25 V, R
A max
A max
A max
A max
Conditions/Comments
Address to WR Setup Time
Address to WR Hold Time
Data Valid to WR Setup Time
Data Valid to WR Hold Time
Write Pulse Width
L
= 2 k , C
SS
Conditions/Comments
Guaranteed Monotonic
For Specified Performance
= 0 V or –5 V
L
AD7228A
= 100 pF
10%)