HI5660/16IA INTERSIL [Intersil Corporation], HI5660/16IA Datasheet

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HI5660/16IA

Manufacturer Part Number
HI5660/16IA
Description
8-Bit, 165/125/60MSPS, High Speed D/A Converter
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
8-Bit, 165/125/60MSPS, High Speed D/A
Converter
The HI5660 is an 8-bit, 125MSPS, high speed, low power,
D/A converter which is implemented in an advanced CMOS
process. Operating from a single +3V to +5V supply, the
converter provides 20mA of full scale output current and
includes edge-triggered CMOS input data latches. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented current source architecture. For
an equivalent performance dual version, see the HI5628.
This device complements the CommLink™ HI5X60 family of
high speed converters offered by Intersil, which includes 8,
10, 12, and 14-bit devices.
Ordering Information
HI5660/16IB
HI5660/16IA
HI5660IB
HI5660IA
HI5660/6IB
HI5660/6IA
HI5660EVAL1
Contact factory for availability.
NUMBER
PART
-40 to 85 28 Ld SOIC
-40 to 85 28 Ld TSSOP M28.173 165MHz
-40 to 85 28 Ld SOIC
-40 to 85 28 Ld TSSOP M28.173 125MHz
-40 to 85 28 Ld SOIC
-40 to 85 28 Ld TSSOP M28.173 60MHz
RANGE
TEMP.
(
o
25
C)
Evaluation Platform
PACKAGE
1
Data Sheet
M28.3
M28.3
M28.3
PKG.
NO.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
165MHz
125MHz
60MHz
125MHz
CLOCK
SPEED
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .125MSPS
• Low Power . . . . . . . . . . . . . . . 165mW at 5V, 27mW at 3V
• Power Down Mode . . . . . . . . . . 23mW at 5V, 10mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . 0.25 LSB
• Adjustable Full Scale Output Current . . . . . 2mA to 20mA
• SFDR to Nyquist at 10MHz Output . . . . . . . . . . . . .60dBc
• Internal 1.2V Bandgap Voltage Reference
• Single Power Supply from +5V to +3V
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
Applications
• Medical Instrumentation
• Wireless Communications
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• Test Instrumentation
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
Pinout
1-888-INTERSIL or 321-724-7143
November 1999
D7 (MSB)
D0 (LSB)
DCOM
DCOM
DCOM
DCOM
DCOM
DCOM
D6
D5
D4
D3
D2
D1
10
11
12
13
14
1
2
3
4
5
6
7
8
9
HI5660 (SOIC, TSSOP)
CommLink™ is a trademark of Intersil Corporation.
TOP VIEW
|
Copyright
File Number
©
Intersil Corporation 1999
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK
DV
DCOM
NC
AV
NC
IOUTA
IOUTB
ACOM
COMP1
FSADJ
REFIO
REFLO
SLEEP
HI5660
DD
DD
4521.4

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HI5660/16IA Summary of contents

Page 1

... Ordering Information TEMP. PART RANGE o NUMBER ( C) PACKAGE † HI5660/16IB - SOIC † HI5660/16IA - TSSOP M28.173 165MHz HI5660IB - SOIC † HI5660IA - TSSOP M28.173 125MHz † HI5660/6IB - SOIC HI5660/6IA - TSSOP M28.173 60MHz † ...

Page 2

Typical Applications Circuit DCOM FERRITE BEAD + 0.1 F Functional Block Diagram (LSB LATCH (MSB) D7 CLK AV ACOM DV ...

Page 3

... LSB, equivalent to 8 Bits) (Note 7) Singlet Glitch Area (Peak Glitch) R Output Rise Time Full Scale Step Output Fall Time Full Scale Step Output Capacitance Output Noise IOUTFS = 20mA IOUTFS = 2mA AC CHARACTERISTICS HI5660/16IB, HI5660/16IA - 165MHz Spurious Free Dynamic Range, f CLK SFDR Within a Window f CLK f CLK f CLK ...

Page 4

Electrical Specifications AV DD PARAMETER Total Harmonic Distortion (THD CLK Nyquist f CLK Spurious Free Dynamic Range, f CLK SFDR to Nyquist f CLK f CLK f CLK f CLK f CLK f CLK AC CHARACTERISTICS HI5660IB, HI5660IA ...

Page 5

Electrical Specifications AV DD PARAMETER Input Logic Low Voltage with (Note 3) 5V Supply Input Logic Low Voltage with (Note 3) 3V Supply Input Logic Current Input Logic Current Digital Input Capacitance, ...

Page 6

Timing Diagrams CLK D7-D0 I OUT t SETT t PD FIGURE 1. OUTPUT SETTLING TIME DIAGRAM CLK t SU D7-D0 I OUT t PD FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 6 HI5660 50% ...

Page 7

Definition of Specifications Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Differential Linearity Error, DNL, is the measure of the step ...

Page 8

Ground Plane(s) If separate digital and analog ground planes are ...

Page 9

Pin Descriptions PIN NO. PIN NAME 1-8 D7 (MSB) Through D0 (LSB) 9-14 DCOM 15 SLEEP 16 REFLO 17 REFIO 18 FSADJ 19 COMP1 20 ACOM 21 IOUTB 22 IOUTA DCOM 27 ...

Page 10

Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX 0.25(0.010) E AREA E1 - 0.05(0.002) SEATING PLANE - - 0.10(0.004) 0.10(0.004 NOTES: 1. These package dimensions ...

Page 11

Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - - 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the “MO ...

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