PCA9512AD ETC1 [List of Unclassifed Manufacturers], PCA9512AD Datasheet - Page 6

• Manufacturer Part Number: PCA9512AD
• Description: Level shifting hot swappable I2C-bus and SMBus bus buffer
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Philips Semiconductors
PCA9512A_1
Product data sheet
8.4 Propagation delays
The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise
time accelerator can be turned off) are a little different with the rise time accelerator turned
off because the rise time accelerator will not pull the node up, but the same logic that turns
on the accelerator turns the pull-down off. If the V
detected, the pull-down will turn off and will not turn back on until a falling edge is
detected.
Consider a system with three buffers connected to a common node and communication
between the Master and Slave B that are connected at either end of buffer A and buffer B
in series as shown in
V
Slave B and then from Slave B to Master. Before the direction change you would observe
V
of buffer B and buffer C would be 0.5 V, but Slave B is driving 0.4 V, so the voltage at
Slave B is 0.4 V. The output of buffer C is 0.5 V. When the Master pull-down turns off, the
input of buffer A rises and so does its output, the common node, because it is the only part
driving the node. The common node will rise to 0.5 V before buffer B's output turns on, if
the pull-up is strong the node may bounce. If the bounce goes above the threshold for the
rising edge accelerator 0.6 V the accelerators on both buffer A and buffer C will fire
contending with the output of buffer B. The node on the input of buffer A will go HIGH as
will the input node of buffer C. After the common node voltage is stable for a while the
rising edge accelerators will turn off and the common node will return to 0.5 V because
the buffer B is still on. The voltage at both the Master and Slave C nodes would then fall to
the return to 0.5 V on the common node ( 0.6 V at the Master and Slave C) occurred
before the data setup time. If this were the SCL line, the parts on buffer A and buffer C
would see a false clock rather than a stretched clock, which would cause a system error.
The delay for a rising edge is determined by the combined pull-up current from the bus
resistors and the rise time accelerator current source and the effective capacitance on the
lines. If the pull-up currents are the same, any difference in rise time is directly
proportional to the difference in capacitance between the two sides. The t
negative if the output capacitance is less than the input capacitance and would be positive
if the output capacitance is larger than the input capacitance, when the currents are the
same.
The t
below 0.7V
non-zero delay, and the output has a limited maximum slew rate, and even if the input slew
0.6 V until Slave B turned off. This would not cause a failure on the data line as long as
Fig 4. System with 3 buffers connected to common node
OL
IL
at the input of buffer A of 0.3 V and its output, the common node, is 0.4 V. The output
of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to
PHL
can never be negative because the output does not start to fall until the input is
CC
(or 0.7V
Figure
CC2
Rev. 01 — 7 October 2005
MASTER
Level shifting hot swappable I
for SDAOUT and SCLOUT), and the output turn on has a
4. Consider if the V
buffer A
common
node
OL
buffer C
buffer B
IL
at the input of buffer A is 0.3 V and the
is above 0.6 V and a rising edge is
2
SLAVE C
SLAVE B
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
C-bus and SMBus bus buffer
002aab581
PCA9512A
PLH
may be
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