AS8530-ASOT AMSCO [austriamicrosystems AG], AS8530-ASOT Datasheet - Page 17

• Manufacturer Part Number: AS8530-ASOT
• Description: LIN Transceiver with Integrated Voltage Regulator and MCU Interface for Automotive Applications
• Manufacturer: AMSCO [austriamicrosystems AG]

AS8530
Preliminary Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
8 Application Information
8.1 Initialization
When the power supply is switched on, if VSUP > VSUVR_OFF, RESET_VSUP_N becomes inactive (high). After this, the voltage regulator
starts with a default LDO output setting of 3.3V and Vuvr_off setting of 2.75V. If V
The rising edge of PORN_2_OTP loads contents of fuse onto the OTP latch after load access time T
contents of OTP latch onto the pre-regulator domain register. This register gives actual settings of LDO, Vuvr_off and Reset Timeout period T
This is done because the OTP block is powered by the V
asserted after Reset Timeout period T
slow ramp rates on VSUP (of the order of 0.5V/min).
Figure 7. Initialization Sequence for AS8530
Table 13. VSUP>Vsuvr_on and V
Table 14. VSUP<Vsuvr_on
www.austriamicrosystems.com/Lin_CompanionIC/AS8530
TRANSCEIVER = Enabled (disabled only during initial VSUP ramp-up)
VSUP
Settings
LDO = Enabled (disabled only during initial ramp-up)
LOAD_OTP_IN_P
Device
RESET_VSUP_N
RESET
VSUP_POR_Threshold = 3.1V
VCC
PORN_2_OTP
RESET_VCC_N
REREG
LDO Off
RESISTIVE DIVIDER = Enabled
TRANSCEIVER = Disabled
RELAY DRIVER = Disabled
RELAY DRIVER = Enabled
VCC_POR_Threshold = 2.75V
CC
RESET = Enabled
LDO = Disabled
<Vuvr_on
Res
VCC Por Threshold = 2.75V
Reset Timeout = 4msec
LDO setting = 3.3V
Block
Block
PHASE 1
(phase 2) and then device enters into normal mode. The circuit also needs to initialize correctly for very
LDO On
RC-Oscillator
6 Cycles of
CC
. If V
CC
Revision 0.01
If Phase 1 POR threshold == Phase 2 POR threshold
> Vuvr_off (phase 2), Reset timeout is restarted. RESET signal is de-
VCC Por Threshold = from OTP Block
Reset Timeout = from OTP Block
LDO setting = from OTP Block
Tres = Reset Timeout from OTP Block
If Phase 1 POR threshold != Phase 2 POR threshold
LDO On
Tres = Reset Timeout from OTP Block
CC
PHASE 2
> Vuvr_off (2.75V), active-low PORN_2_OTP is generated.
VBAT= high, VBAT_DIV = enabled
LDRIVE1 = high, LDRIVE2 = high
LDRIVE1 = high, LDRIVE2 = high
Load
LIN = high-z, RX = follows V
LIN = high-z, RX = high-z
. LOAD_OTP_IN_PREREG signal loads
RESET = high-z
Output Signal
Output Signal
V
V
CC
CC
= low
= low
17 - 29
Res
.