ADV7129KS AD [Analog Devices], ADV7129KS Datasheet - Page 12

• Manufacturer Part Number: ADV7129KS
• Description: 192-Bit, 360 MHz True-Color Video DAC with Onboard PLL
• Manufacturer: AD [Analog Devices]

ADV7129
COMMAND REGISTER 2 (CR2)
(Address Register (A10–A0) = 411H)
This register contains a number of control bits as shown in the
diagram. CR2 is an 8-bit wide register. CR27, CR24, CR22
and CR21 are reserved and should be set to logic “0.” Figure 8
shows the various operations under the control of CR2. This
register can be read from as well as written to.
COMMAND REGISTER 2-BIT DESCRIPTION
PLL Control (CR20)
This bit resets the PLL divider when set to logic “0” and re-
leases it when set to logic “1.”
SYNCOUT Control (CR23)
This bit is an enable for SYNCOUT. If this bit is set to logic
“1,” the SENSE output becomes a pipelined version of
CSYNC. Otherwise the SENSE output remains unaffected.
SENSE Bit (CR25)
This output bit is used to determine the absence of a CRT
monitor. When CR25 is set to logic “1,” a CRT is not present.
With some diagnostic code, the presence of loading on the indi-
vidual RGB lines can be determined. The reference is generated
by a voltage divider from the external voltage reference on the
V
be applied to the comparator by the IOR, IOG and IOB outputs:
RE F
DAC Low Voltage
DAC High Voltage
pin. For the proper operation, the following levels should
GR07
0
1
THIS BIT SHOULD BE
SET TO LOGIC “0”
250 mV.
450 mV.
RESERVED
(CR27)
DISABLE GAIN ERROR ADJ
ENABLE GAIN ERROR ADJ
CR27
GAIN ERROR
CONTROL
CR26
0
1
GR07
VCO OVERRIDE
VCO OVERRIDE
NORMAL PLL
OPERATION
CR26
DACs
R
SET
CR25
GR06
0
1
SENSE OUTPUT
1
MONITOR
PRESENT
MONITOR
NOT PRESENT
Figure 8. Command Register 2
CR25
Figure 9. Gain Error Register
R
6
x
GAIN ERROR REGISTER
GR05
THIS BIT SHOULD BE
INTERNAL RESISTORS
R
SET TO LOGIC “0”
x
5
RESERVED
R
(CR24)
4
CR24
x
R
x
3
–12–
GR04
SYNCOUT CONTROL
CR23
0
1
R
2
x
VCO Override Bit (CR26)
This bit is used to override the VCO and set the PLL to the
lowest frequency possible. If the external LOADIN source takes
some time before it reaches its required frequency, the internal
PLL can become unstable as it tries to track to a varying
LOADIN signal. The VCO override bit can be set to logic level
“0” and then released (set to logic level “1”) to allow the VCO
to track to the input after it has stabilized. It is required to allow
200 s before the VCO override bit is released.
GAIN ERROR REGISTERS
(Address Register (A10–A0) = 405H–407H)
The Red, Green and Blue Gain Error Registers allow the user to
compensate for any channel-to-channel variations in the video
output system. They control internal resistors from each of the
three DAC outputs to GND, i.e., they appear in parallel with
the external termination resistor across the DAC outputs. This
allows the RGB output voltages to be adjusted as the value of
R
GR00 switches in the appropriate resistor. A logic “0” disables
or open circuits the resistor. Bit GR07 of the Gain Error
Register enables or disables the Gain Error Adjust. Figure 9
shows the typical resistor values for these internal resistances
versus R
R
CR23
INT
1
x
IGNORE
DECODE
REGISTER
GR06 R6
GR05 R5
GR04 R4
GR03 R3
GR02 R2
GR01 R1
GR00 R0
R
is varied. A logic “1” on any of the control bits GR06 to
0
x
GR03
SET
THESE BITS SHOULD BE
CR22
I
.
OUT
SET TO LOGIC “0”
(RESET = 280 )
PIN
(CR22, CR21)
RESERVED
GR02
16610
27037
1926
3476
6979
923
47
R
CR21
T1
(CABLE)
CR20
GR01
0
1
PLL RESET
R
T2
RESET PLL
RELEASE PLL
CR20
(MONITOR)
GR00
REV. 0