X9448-2.7 XICOR [Xicor Inc.], X9448-2.7 Datasheet - Page 4

• Manufacturer Part Number: X9448-2.7
• Description: Mixed Signal with 2-Wire Interface
• Manufacturer: XICOR [Xicor Inc.]

X9448
Voltage Comparator
The comparator compares the wiper voltage V
the external input voltage V
logic level output are controlled by the Shutdown,
Latch, and Enable bits of the analog control register
(ACR). Enable connects the comparator output to the
V
Shutdown removes the analog section supply voltages
to save power. The analog control register is pro-
grammed using the two wire serial interface.
The ACR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the ACR. These data registers and
the ACR may be read and written by the host system.
INSTRUCTIONS AND PROGRAMMING
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9448 this
is fixed as 0101[B].
Figure 1. Address/Identification Byte Format
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9448 compares the
serial data stream with the address input state; a suc-
cessful compare of all four address bits is required for
the X9448 to respond with an acknowledge. The A
A
nals or tied to V
Acknowledge Polling
The disabling of the inputs, during the internal nonvol-
atile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9448 initiates the internal
REV 1.0 6/21/00
OUT
3
inputs can be actively driven by CMOS input sig-
pin, Latch memorizes the output logic state, and
0
Device Type
Identifier
1
CC
or V
0
SS
1
.
NI
A3
. The comparator and its
Device Address
A2
A1
A0
W
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with
0
–
write cycle. ACK polling (Flow 1) can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9448 is
still busy with the write operation no ACK will be
returned. If the X9448 has completed the write opera-
tion an ACK will be returned and the master can then
proceed with the next operation.
Flow 1. ACK Polling Sequence
Instruction Structure
The byte following the address contains the instruction
and register pointer information. The four most signifi-
cant bits are the instruction. The next four bits point to
one of two pots or one of two voltage comparators and
when applicable they point to one of four associated
registers. The format is shown below in Figure 2.
Figure 2. Instruction Byte Format
I3
Command Completed
Enter ACK Polling
Nonvolatile Write
Instructions
I2
Issue Slave
PROCEED
Returned?
Instruction
Operation
START
Address
Further
Issue
Issue
ACK
I1
YES
YES
Characteristics subject to change without notice.
I0
NO
NO
Register
R1
Select
WCR and ACR Select
R0
Issue STOP
P1
PROCEED
Issue STOP
P0
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