DAC8412BTC/883 AD [Analog Devices], DAC8412BTC/883 Datasheet - Page 10

• Manufacturer Part Number: DAC8412BTC/883
• Description: Quad, 12-Bit DAC Voltage Output with Readback
• Manufacturer: AD [Analog Devices]

DAC8412/DAC8413
OPERATION
Introduction
The DAC8412 and DAC8413 are quad, voltage output, 12-bit
parallel input DACs featuring a 12-bit data bus with readback
capability. The only differences between the DAC8412 and
DAC8413 are the reset functions. The DAC8412 resets to mid-
scale (code 800
(code 000
The ability to operate from a single +5 V supply is a unique fea-
ture of these DACs.
Operation of the DAC8412 and DAC8413 can be viewed by
dividing the system into three separate functional groups: the
digital I/O and logic, the digital to analog converters and the output
amplifiers.
DACs
Each DAC is a voltage switched, high impedance (R = 50 kΩ),
R-2R ladder configuration. Each 2R resistor is driven by a pair of
switches that connect the resistor to either V
Glitch
Worst-case glitch occurs at the transition between half-scale
digital code 1000 0000 0000 to half-scale minus 1 LSB, 0111
1111 1111. It can be measured at about 2 V µs. (See Figure 33.)
For demanding applications such as waveform generation or
0.001
10.0
1.00
0.10
0.01
Figure 29. DAC8412 Noise
Frequency vs. Noise Density
1
H
).
NOISE FREQUENCY – Hz
10
H
) and the DAC8413 resets to minimum scale
100
V
V
V
V
T
–10
–15
–20
–25
DD
SS
REFH
REFL
A
25
20
15
10
–5
1000
5
0
= +25 C
–6
= +15V
= –15V
= –10V
= +10V
V
V
V
V
T
DATA = 800
Figure 32. I
DD
SS
REFH
REFL
A
–I
= +25 C
–4
= 0V
= +15V
SC
10000
= 0V
= +10V
–2
H
V
OUT
REFH
OUT
– Volts
0
vs. V
–10
–20
–30
or V
+I
30
20
10
–25 –20
0
0
0
2
SC
V
V
V
V
T
DATA = 000
OUT
REFL
Figure 30. I
A
DD
SS
REFH
REFL
= +25 C
4
= –15V
= +15V
–15
–I
.
= +10V
= –10V
SC
–10
6
H
V
–10–
–5
OUT
OUT
– Volts
0
Figure 33. Glitch and Deglitched Results
precision instrumentation control, a deglitcher circuit can be
implemented with a standard sample-and-hold circuit. (See
Figure 34.) When CS is enabled by synchronizing the hold
period to be longer than the glitch tradition, the output voltage
can be smoothed with minimum disturbance. A quad sample-
and-hold amplifier, SMP04, has been used to illustrate the
deglitching result. (See Figure 33.)
vs. V
5
2
1
10
DACOUT'
DACOUT
+I
OUT
1V
1V
SC
15
S/H
CS
20
S/H
DACOUT
DEGLITCHER OUTPUT
25
GLITCH AT DAC OUTPUT
Figure 34. Deglitcher Circuit
10 s
1
20uV/DIV
H
Figure 31. Broadband Noise
CH2
4 s
1.86V
S
M 200 s
H
DACOUT'
A CH1
REV. D
S
12.9mV
V
V
V
V
T
DD
SS
REFH
REFL
A
CH1 MEAN
= +25 C
66.19 V
= +15V
= –15V
= –10V
= +10V