DAC8420QBC AD [Analog Devices], DAC8420QBC Datasheet - Page 6

• Manufacturer Part Number: DAC8420QBC
• Description: Quad 12-Bit Serial Voltage Output DAC
• Manufacturer: AD [Analog Devices]

DAC8420
Power Supplies
Clock
Control Inputs
Data Input
Reference Inputs
Analog Outputs
VREFLO
VREFHI
VOUTD
VOUTC
VOUTB
VOUTA
VDD
VSS
VDD: Positive Supply, +5 V to +15 V.
VSS: Negative Supply, 0 V to –15 V.
GND: Digital Ground.
CLK: System Serial Data Clock Input, TTL/CMOS levels. Data presented to the input SDI is shifted into
the internal serial-parallel input register on the rising edge of clock. This input is logically ORed with CS.
(All are CMOS/TTL compatible.)
CLR: Asynchronous Clear, active low. Sets internal data registers A-D to zero or midscale, depending on cur-
rent state of CLSEL. The data in the serial input shift register is unaffected by this control.
CLSEL: Determines action of CLR. If HIGH, a Clear command will set the internal DAC registers A-D to
midscale (800
CS: Device Chip Select, active low. This input is logically ORed with the clock and disables the serial data
register input when HIGH. When LOW, data input clocking is enabled, see the Control Function Table.
LD: Asynchronous DAC Register Load Control, active low. The data currently contained in the serial input
shift register is shifted out to the DAC data registers on the falling edge of LD, independent of CS. Input data
must remain stable while LD is LOW.
(All are CMOS/TTL compatible.)
SDI: Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register, which
shifts data in beginning with DAC address Bit A1. This input is ignored when CS is HIGH.
The format of the 16-bit serial word is:
(FIRST)
B0
A1
—Address Word—
NC = Don’t Care.
VREFHI: Upper DAC ladder reference voltage input. Allowable range is (V
VREFLO: Lower DAC ladder reference voltage input, equal to zero scale output. Allowable range is V
(V
VOUTA through VOUTD: Four buffered DAC voltage outputs.
1
2
4
3
7
8
5
6
VREFHI
NC = NO CONNECT
(Not to Scale)
DAC8420
A0
B1
TOP VIEW
DIP
– 2.5 V).
B2
NC
H
). If LOW, the registers are set to zero (000
16
15
14
13
12
10
11
9
B3
NC
CLK
CLSEL
CLR
LD
NC
SDI
GND
CS
(MSB)
D11 D10 D9
PIN FUNCTION DESCRIPTION
B4
PIN CONFIGURATIONS
B5
B6
–6–
—DAC Data Word—
D8
B7
B8
D7
H
).
B9
D6
VREFLO
VREFHI
VOUTD
VOUTC
VOUTB
VOUTA
VDD
VSS
D5
B10
NC = NO CONNECT
1
2
3
4
6
8
5
7
DD
DAC-8420
(Not to Scale)
DAC-8420
(Not to Scale)
(Not to Scale)
DAC8420
TOP VIEW
B11
D4
TOP VIEW
TOP VIEW
– 2.5 V) to (V
SOL
B12
D3
15
14
13
12
11
10
16
9
B13
D2
VREFLO
CLSEL
CLR
CLK
GND
LD
NC
CS
SDI
B14
D1
+2.5 V).
(LSB)
(LAST)
SS
B15
D0
REV. 0
to