CY37000 CYPRESS [Cypress Semiconductor], CY37000 Datasheet

CY37000

Manufacturer Part Number

CY37000

Description

5V, 3.3V, ISR High-Performance CPLDs

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

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Cypress Semiconductor Corporation

Document #: 38-03007 Rev. **

Features

Note:

• In-System Reprogrammable™ (ISR™) CMOS CPLDs

• High density

• Simple timing model

• 3.3V and 5V versions

• PCI Compatible

• Programmable Bus-Hold capabilities on all I/Os

• Intelligent product term allocator provides:

• Flexible clocking

• Consistent package/pinout offering across all densities

• Packages

— JTAG interface for reconfigurability

— Design changes don’t cause pinout changes

— Design changes don’t cause timing changes

— 32 to 512 macrocells

— 32 to 264 I/O pins

— 5 dedicated inputs including 4 clock pins

— No fanout delays

— No expander delays

— No dedicated vs. I/O pin delays

— No additional delay through PIM

— No penalty for using full 16 product terms

— No delay for steering or sharing product terms

— 0 to 16 product terms to any macrocell

— Product term steering on an individual basis

— Product term sharing among local macrocells

— 4 synchronous clocks per device

— Product Term clocking

— Clock polarity control per logic block

— Simplifies design migration

— Same pinout for 3.3V and 5.0V devices

— 44 to 400 Leads in PLCC, CLCC, PQFP, TQFP, CQFP,

Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V

BGA, and Fine-Pitch BGA packages

[1]

5V, 3.3V, ISR™ High-Performance CPLDs

•

3901 North First Street

General Description

The Ultra37000™ family of CMOS CPLDs provides a range of

high-density programmable logic solutions with unparalleled

system performance. The Ultra37000 family is designed to

bring the flexibility, ease of use, and performance of the 22V10

to high-density CPLDs. The architecture is based on a number

of logic blocks that are connected by a Programmable Inter-

connect Matrix (PIM). Each logic block features its own prod-

uct term array, product term allocator, and 16 macrocells. The

PIM distributes signals from the logic block outputs and all in-

put pins to the logic block inputs.

All of the Ultra37000 devices are electrically erasable and In-

System Reprogrammable (ISR), which simplifies both design

and manufacturing flows, thereby reducing costs. The ISR fea-

ture provides the ability to reconfigure the devices without hav-

ing design changes cause pinout or timing changes. The

Cypress ISR function is implemented through a JTAG-compli-

ant serial interface. Data is shifted in and out through the TDI

and TDO pins, respectively. Because of the superior routability

and simple timing model of the Ultra37000 devices, ISR allows

users to change existing logic designs while simultaneously

fixing pinout assignments and maintaining system perfor-

mance.

The entire family features JTAG for ISR and boundary scan,

and is compatible with the PCI Local Bus specification, meet-

ing the electrical and timing requirements. The Ultra37000

family features user programmable bus-hold capabilities on all

I/Os.

Ultra37000 5.0V Devices

The Ultra37000 devices operate with a 5V supply and can sup-

port 5V or 3.3V I/O levels. V

pability of interfacing to either a 5V or 3.3V bus. By connecting

the V

outputs. If V

3.3V JEDEC standard CMOS levels and are 5V tolerant.

These devices require 5V ISR programming.

Ultra37000V 3.3V Devices

Devices operating with a 3.3V supply require 3.3V on all V

pins, reducing the device’s power consumption. These devices

support 3.3V JEDEC standard CMOS output levels, and are

5V tolerant. These devices allow 3.3V ISR programming.

, PCI V

CCO

•

=2V.

pins to 5V the user insures 5V TTL levels on the

San Jose

Ultra37000™ CPLD Family

CCO

is connected to 3.3V the output levels meet

•

CA 95134

CCO

connections provide the ca-

Revised March 15, 2001

•

408-943-2600

CCO

Related parts for CY37000

CY37000 Summary of contents

Page 1

Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes • High density — 512 macrocells — 264 I/O pins ...

Page 2

Selection Guide 5.0V Selection Guide General Information Device Macrocells CY37032 32 CY37064 64 CY37128 128 CY37192 192 CY37256 256 CY37384 384 CY37512 512 Speed Bins Device 200 167 CY37032 X CY37064 X CY37128 X CY37192 CY37256 CY37384 CY37512 Device-Package Offering ...

Page 3

Selection Guide General Information Device Macrocells CY37032V 32 CY37064V 64 CY37128V 128 CY37192V 192 CY37256V 256 CY37384V 384 CY37512V 512 Speed Bins Device 200 167 CY37032V CY37064V CY37128V CY37192V CY37256V CY37384V CY37512V Shaded areas indicate preliminary speed bins. Device-Package ...

Page 4

Architecture Overview of Ultra37000 Family Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interconnection to avoid fitting ...

Page 5

Low-Power Option Each logic block can operate in high-speed mode for critical path performance low-power mode for power conserva- tion. The logic block mode is set by the user on a logic block by logic block basis. Product ...

Page 6

FROM PTM 0 16 PRODUCT TERMS FROM PTM 0 16 PRODUCT TERMS ASYNCHRONOUS BLOCK RESET 4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3) ASYNCHRONOUS 1 ASYNCHRONOUS CLOCK(PTCLK) BLOCK PRESET FROM CLOCK POLARITY MUXES Document #: 38-03007 Rev. ** I/O MACROCELL 0 1 C25 ...

Page 7

INPUT/CLOCK PIN 0 FROM CLOCK 1 O POLARITY INPUT 2 CLOCK PINS Clocking Each I/O and buried macrocell has access to four synchronous clocks (CLK0, CLK1, CLK2 and CLK3) as well as an asynchro- nous product term ...

Page 8

IEEE 1149.1 Compliant JTAG The Ultra37000 family has an IEEE 1149.1 JTAG interface for both Boundary Scan and ISR. Boundary Scan The Ultra37000 family supports Bypass, Sample/Preload, Ex- test, Idcode, and Usercode boundary scan instructions. The JTAG interface is shown ...

Page 9

Logic Block Diagrams CY37032 / CY37032V 16 I/Os I/O I CY37064 / CY37064V (100-Lead TQFP) 16 I/Os I/O -I I/Os I/O -I TDI JTAG Tap TCK TDO Controller TMS Document #: 38-03007 Rev. ...

Page 10

Logic Block Diagrams (continued) CY37128 / CY37128V (160-Lead TQFP) 16 I/Os I/O –I I/Os I/O –I I/Os I/O –I I/Os I/O –I CY37192 / CY37192V (160-Lead TQFP) 10 I/Os ...

Page 11

Logic Block Diagrams (continued) CY37256 / CY37256V (256-Lead BGA) 12 I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I ...

Page 12

Logic Block Diagrams (continued) CY37384 / CY37384V (256-Lead BGA) 12 I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I ...

Page 13

Logic Block Diagrams (continued) CY37512 / CY37512V (352-Lead BGA) 12 I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I ...

Page 14

Device Characteristics Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V ...

Page 15

Device Electrical Characteristics Parameter Description V Output HIGH Voltage OH V Output HIGH Voltage with OHZ [5] Output Disabled V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Load Current IX ...

Page 16

Device Characteristics Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. – +150 C Ambient Temperature with Power Applied............................................. – +125 C Supply Voltage to ...

Page 17

Capacitance Parameter Description C Input/Output Capacitance I/O C Clock Signal Capacitance CLK C Dual Functional Pins DP [5] Endurance Characteristics Parameter Description N Minimum Reprogramming Cycles AC Characteristics. 5.0V AC Test Loads and Waveforms 238 (COM’L) 319 (MIL) 5V ...

Page 18

Parameter t ER(–) t ER(+) t EA(+) t EA(–) Note: 10. t measured with 5-pF AC Test Load and t ER Document #: 38-03007 Rev Output Waveform—Measurement Level X 1. 0.5V 2.6V 0. ...

Page 19

Switching Characteristics Over the Operating Range Parameter Combinatorial Mode Parameters [12, 13, 14] t Input to Combinatorial Output PD [12, 13, 14] t Input to Output Through Transparent Input or Output Latch PDL [12, 13, 14] t Input to Output ...

Page 20

Switching Characteristics Over the Operating Range Parameter Operating Frequency Parameters f Maximum Frequency with Internal Feedback (Lesser of 1/t MAX1 f Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(t MAX2 1/( 1/t S ...

Page 21

Switching Characteristics Over the Operating Range 200 MHz 167 MHz 154 MHz Parameter Combinatorial Mode Parameters [12, 13, 14 6.5 PD [12, 13, 14 12.5 PDL [12, 13, 14 13.5 PDLL [12, 13, 14] ...

Page 22

Switching Characteristics Over the Operating Range 200 MHz 167 MHz 154 MHz Parameter Reset/Preset Parameters [12 [12, 13, 14 [12 ...

Page 23

Switching Waveforms Combinatorial Output INPUT COMBINATORIAL OUTPUT Registered Output with Synchronous Clocking INPUT SYNCHRONOUS CLOCK REGISTERED OUTPUT REGISTERED OUTPUT SYNCHRONOUS CLOCK Registered Output with Product Term Clocking Input Going Through the Array INPUT PRODUCT TERM CLOCK REGISTERED OUTPUT Document #: ...

Page 24

Switching Waveforms (continued) Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register INPUT PRODUCT TERM CLOCK REGISTERED OUTPUT Latched Output INPUT LATCH ENABLE LATCHED OUTPUT Registered Input REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK Document #: ...

Page 25

Switching Waveforms (continued) Clock to Clock INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Document #: ...

Page 26

Switching Waveforms (continued) Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS Document #: 38-03007 Rev. ** Ultra37000™ CPLD Family ...

Page 27

Power Consumption Typical 5.0V Power Consumption CY37032 CY37064 ...

Page 28

Typical 5.0V Power Consumption (continued) CY37128 The typical pattern is a 16-bit up counter, per logic ...

Page 29

Typical 5.0V Power Consumption (continued) CY37256 The typical pattern is a 16-bit up counter, per logic block, with outputs ...

Page 30

Typical 5.0V Power Consumption (continued) CY37512 Typical 3.3V Power Consumption CY37032V ...

Page 31

Typical 3.3V Power Consumption (continued) CY37064V The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. CY37128V ...

Page 32

Typical 3.3V Power Consumption (continued) CY37192V The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. CY37256V ...

Page 33

Typical 3.3V Power Consumption (continued) CY37384V The typical pattern is ...

Page 34

Pin Configurations I/O CLK JTAG CLK Note: 19. For 3.3V versions (Ultra37000V CCO Document #: 38-03007 Rev. ** 44-Pin TQFP (A44) Top View /TCK 5 I/O ...

Page 35

Pin Configurations (continued) Document #: 38-03007 Rev. ** 48-Ball Fine-Pitch BGA (BA50) Top View I/O V I/O I/O I/O I TCK B V I/O I/O I/O ...

Page 36

Pin Configurations (continued I I I/O /TCK 10 15 I I CLK / CCO GND ...

Page 37

Pin Configurations (continued) 100 99 98 TCK 1 GND CLK / ...

Page 38

Pin Configurations (continued I/O C I/O D I/O E I/O F I/O G I I/O C I/O D I/O E I/O F I/O G I/O H I/O ...

Page 39

Pin Configurations (continued) GND I I/O /TCK GND I I I/O ...

Page 40

Pin Configurations (continued) GND I I TCK GND I/O ...

Page 41

Pin Configurations (continued) GND I TCK I I I/O 29 GND 13 ...

Page 42

Pin Configurations (continued GND I/O NC I/O I/O I I/O I/O I/O I/O I/O I I/O NC I/O I ...

Page 43

Pin Configurations (continued GND GND I/O I GND I/O I/O I I/O I I/O I/O I I/O I/O I/O I/O ...

Page 44

Pin Configurations (continued GND GND I/O I/O I/O I/O I GND NC I/O I/O I/O I/O I I/O I/O ...

Page 45

Pin Configurations (continued) A GND GND NC I/O I GND GND GND NC I GND GND GND I I/O NC GND I/O I I/O I/O I/O I/O ...

Page 46

Ordering Information Cypress Semiconductor ID Family Type 37 = Ultra37000 Family Macrocell Density Macrocells 256 = 256 Macrocells 64 ...

Page 47

Ordering Information (continued) Macro- Speed cells (MHz) Ordering Code 64 200 CY37064P44-200AC CY37064P44-200JC CY37064P84-200JC CY37064P100-200AC 154 CY37064P44-154AC CY37064P44-154JC CY37064P84-154JC CY37064P100-154AC CY37064P44-154AI CY37064P44-154JI CY37064P84-154JI CY37064P100-154AI 5962-9951902QYA 125 CY37064P44-125AC CY37064P44-125JC CY37064P84-125JC CY37064P100-125AC CY37064P44-125AI CY37064P44-125JI CY37064P84-125JI CY37064P100-125AI 5962-9951901QYA 128 167 CY37128P84-167JC CY37128P100-167AC ...

Page 48

Ordering Information (continued) Macro- Speed cells (MHz) Ordering Code 192 154 CY37192P160-154AC 125 CY37192P160-125AC CY37192P160-125AI 83 CY37192P160-83AC CY37192P160-83AI 256 154 CY37256P160-154AC CY37256P208-154NC CY37256P256-154BGC 125 CY37256P160-125AC CY37256P208-125NC CY37256P256-125BGC CY37256P160-125AI CY37256P208-125NI CY37256P256-125BGI 5962-9952302QZC 83 CY37256P160-83AC CY37256P208-83NC CY37256P256-83BGC CY37256P160-83AI CY37256P208-83NI CY37256P256-83BGI 5962-9952301QZC ...

Page 49

Ordering Information (continued) Macro- Speed cells (MHz) Ordering Code 512 125 CY37512P208-125NC CY37512P256-125BGC CY37512P352-125BGC 100 CY37512P208-100NC CY37512P256-100BGC CY37512P352-100BGC CY37512P208-100NI CY37512P256-100BGI CY37512P352-100BGI 5962-9952502QZC 83 CY37512P208-83NC CY37512P256-83BGC CY37512P352-83BGC CY37512P208-83NI CY37512P256-83BGI CY37512P352-83BGI 5962-9952501QZC 3.3V Ordering Information Macro- Speed cells (MHz) Ordering Code ...

Page 50

Ordering Information (continued) Macro- Speed cells (MHz) Ordering Code 64 143 CY37064VP44-143AC CY37064VP44-143JC CY37064VP48-143BAC CY37064VP84-143JC CY37064VP100-143AC CY37064VP100-143BBC 100 CY37064VP44-100AC CY37064VP44-100JC CY37064VP48-100BAC CY37064VP84-100JC CY37064VP100-100AC CY37064VP100-100BBC CY37064VP44-100AI CY37064VP44-100JI CY37064VP48-100BAI CY37064VP84-100JI CY37064VP100-100BBI CY37064VP100-100AI 5962-9952001QYA 128 125 CY37128VP84-125JC CY37128VP100-125AC CY37128VP100-125BBC CY37128VP160-125AC 83 CY37128VP84-83JC ...

Page 51

Ordering Information (continued) Macro- Speed cells (MHz) Ordering Code 256 100 CY37256VP160-100AC CY37256VP208-100NC CY37256VP256-100BGC CY37256VP256-100BBC 66 CY37256VP160-66AC CY37256VP208-66NC CY37256VP256-66BGC CY37256VP256-66BBC CY37256VP160-66AI CY37256VP256-66BGI CY37256VP256-66BBI 5962-9952401QZC 384 83 CY37384VP208-83NC CY37384VP256-83BGC 66 CY37384VP208-66NC CY37384VP256-66BGC CY37384VP208-66NI CY37384VP256-66BGI 512 83 CY37512VP208-83NC CY37512VP256-83BGC CY37512VP352-83BGC CY37512VP400-83BBC ...

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