ATF22V10B-10JC ATMEL [ATMEL Corporation], ATF22V10B-10JC Datasheet - Page 5
Manufacturer Part Number
High- Performance EE PLD
ATMEL [ATMEL Corporation]
Input Test Waveforms and
f = 1 MHz, T = 25°C
Power Up Reset
The registers in the ATF22V10Bs are designed to reset
during power up. At a point delayed slightly from V
The output state will depend on the polarity of the output
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
lowing conditions are required:
1. The V
2. After reset occurs, all input and feedback setup times
3. The clock must remain stable during t
Preload of Registered Outputs
The ATF22V10B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
must be met before driving the clock pin high, and
< 3 ns
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
rise must be monotonic,
, all registers will be reset to the low state.
actually rises in the system, the fol-
Outout Test Loads
* All except -7 which is R2 = 300
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF22V10B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect