ADSP-21267SKBCZ-X AD [Analog Devices], ADSP-21267SKBCZ-X Datasheet - Page 20
ADSP-21267SKBCZ-X
Manufacturer Part Number
ADSP-21267SKBCZ-X
Description
Preliminary Technical Data
Manufacturer
AD [Analog Devices]
Datasheet
1.ADSP-21267SKBCZ-X.pdf
(44 pages)
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ADSP-21267
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer[2:0] in
PWM_OUT (pulse width modulation) mode. Timer signals are
routed to the DAI_P[20:1] pins through the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P[20:1] pins.
Table 13. Timer[2:0] PWM_OUT Timing
Timer WDTH_CAP Timing
The following timing specification applies to Timer[2:0] in
WDTH_CAP (pulse width count and capture) mode. Timer sig-
nals are routed to the DAI_P[20:1] pins through the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P[20:1] pins.
Table 14. Timer[2:0] Width Capture Timing
Parameter
Switching Characteristic
t
Parameter
Timing Requirement
t
PWMO
PWI
(TIMER[2:0])
DAI_P[20:1]
(TIMER[2:0])
DAI_P[20:1]
Timer[2:0] Pulse Width Output
Timer[2:0] Pulse Width
PRELIMINARY TECHNICAL DATA
Figure 13. Timer[2:0] Width Capture Timing
Figure 12. Timer[2:0] PWM_OUT Timing
Rev. PrA | Page 20 of 44 | January 2004
Min
2 t
Min
2 t
CCLK
CCLK
t
PWMO
t
PWI
Max
2(2
Max
2(2
31
31
– 1) t
– 1) t
CCLK
CCLK
Unit
ns
Unit
ns
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