ADSP-21366SBSQ-ENG AD [Analog Devices], ADSP-21366SBSQ-ENG Datasheet
ADSP-21366SBSQ-ENG
Related parts for ADSP-21366SBSQ-ENG
ADSP-21366SBSQ-ENG Summary of contents
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... On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21365/6 is available with a 333 MHz core instruc- tion rate and unique audio centric peripherals such as the Digital Audio Interface, S/PDIF transceiver, DTCP (Digital ...
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... ADSP-21365/6 KEY FEATURES – PROCESSOR CORE At 333 MHz (3.0 ns) core instruction rate, the ADSP-21365/6 performs 2 GFLOPS/666 MMACS 3M bit on-chip SRAM (1M Bit in blocks 0 and 1, and 0.50M Bit in blocks 2 and 3) for simultaneous access by the core pro- cessor and DMA 4M bit on-chip mask-programmable ROM (2M bit in block 0 ...
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... Many other SRU configura- Speed tions are possible. (at 333 MHz) ADSP-21365/6 FAMILY CORE ARCHITECTURE 1.5 ns The ADSP-21365/6 is code compatible at the assembly level 6.0 ns with the ADSP-2126x, ADSP-21160 and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-21365/6 shares architectural features with the ADSP- 13.5 ns 2126x and ADSP-2116x SIMD SHARC processors, as detailed 23 ...
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... Instruction Cache The ADSP-21365/6 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This ...
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... Preliminary Technical Data signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-21365/6 con- tain sufficient registers to allow the creation circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce over- head, increase performance, and simplify implementation ...
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... Each data channel has its own DMA channel that is inde- pendent from the ADSP-21365/6's serial ports. For complete information on using the DAI, see the ADSP- 2136x SHARC Processor Hardware Reference. Serial Ports ...
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... DVD Content Scrambling System) will be protected by this copy protection system. This feature is only available on the ADSP-21365 processor. Pulse Width Modulation The PWM module is a flexible, programmable, PWM waveform ...
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... ADSP-21365/6 Timers The ADSP-21365/6 has a total of four timers: a core timer that can generate periodic software interrupts and three general pur- pose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • Pulse Waveform Generation mode • Pulse Width Count /Capture mode • ...
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... Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included Rev. PrA | Page September 2004 ADSP-21365/6 ...
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... EZ-KIT Lite board enables high-speed, non- intrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP- 21365/6 architecture and functionality. For detailed informa- tion on the ADSP-2136x Family core architecture and instruction set, refer to the ADSP-2136x SHARC Processor Hardware Reference and the ADSP-2136x SHARC Processor Programming Reference ...
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... Open Drain, and T = Three-State , (pd) = pulldown resistor, (pu) = pullup resistor. Function Parallel Port Address/Data. The ADSP-21365/6 parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ ...
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... ADSP-21365/6 SPI interaction, any of the master ADSP-21365/6's flag pins can be used to drive the SPIDS signal on the ADSP-21365/6 SPI slave device. SPI Master Out Slave In. If the ADSP-21365/6 is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21365/6 is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data ...
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... Three-state is a three-state driver with pullup disabled. Function Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21365/6 clock input. It configures the ADSP-21365/6 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator ...
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... ADSP-21365/6 ADDRESS DATA PINS AS FLAGS To use these pins as flags (FLAGS15–0) set (=1) bit 20 of the SYSCTL register to disable the parallel port. Then set (=1) bits the SYSCTL register accordingly. Table 4. AD15–0 to Flag Pin Mapping AD Pin Flag Pin AD Pin AD0 ...
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... Preliminary Technical Data ADSP-21365/6 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS 1 Parameter V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT 2 V High Level Input Voltage @ Low Level Input Voltage @ High Level Input Voltage @ V IH_CLKIN ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21365/6 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Figure 5 shows Core to CLKIN ratios of 6:1, 16:1 and 32:1 with external oscillator or crystal. Note that more ratios are possible and can be set through software using the power management control register (PMCTL). For more information, see the ADSP- 2136x SHARC Processor Programming Reference. CLKIN XTAL ...
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... ADSP-21365/6 Power-Up Sequencing The timing requirements for processor startup are given in Table 10. Table 10. Power Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V IVDDEVDD DDINT 1 t CLKIN Valid After V CLKVDD t CLKIN Valid Before RESET Deasserted CLKRST ...
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... CK CLKIN t CKH Figure 7. Clock Input Clock Signals The ADSP-21365/6 can use an external clock or a crystal. See the CLKIN pin description in Table 3 on page mer can configure the ADSP-21365/6 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 8 shows the component connections used for a crystal operating in fundamental mode ...
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... ADSP-21365/6 Reset Table 12. Reset Parameter Timing Requirements 1 t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET is low, assuming 1 stable VDD and CLKIN (not including start-up time of external clock oscillator). ...
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... Parameter Switching Characteristic t Timer Pulse Width Output PWMO DAI_P20-1 (TIMER2-0) Min 4 × t – 1 PCLK t WCTIM Figure 11. Core Timer Min Max 2 t – 1 2(2 PCLK t PWMO Figure 12. Timer PWM_OUT Timing Rev. PrA | Page September 2004 ADSP-21365/6 Max Unit ns Unit 31 – PCLK ...
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... ADSP-21365/6 Timer WDTH_CAP Timing The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specification provided below are valid at the DAI_P20–1 pins. ...
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... All Timing Param- eters and Switching Characteristics apply to external DAI pins (DAI_P07 – DAI_P20). t STRIG t HTRIG t DPCGIO t DTRIG Figure 15. Precision Clock Generator (Direct Pin Routing) Rev. PrA | Page September 2004 ADSP-21365/6 Min Max 2.5 10 2.5 + 2.5 × 2.5 × t PCGOW PCGOW 48 ...
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... ADSP-21365/6 Flags The timing specifications provided below apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface (SPI). See Table 3, “Pin Descriptions,” on page 11 more information on flag use. Table 19. Flags Parameter Timing Requirement t FLAG3–0 IN Pulse Width ...
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... Preliminary Technical Data Memory Read—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the ADSP-21365/6 is accessing external memory space. Table 20. 8-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data 7–0 Setup Before RD High DRS t Address/Data 7–0 Hold After RD High ...
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... ADSP-21365/6 Table 21. 16-bit Memory Read Cycle Parameter Timing Requirements t Address/Data 15–0 Setup Before RD High DRS t Address/Data 15–0 Hold After RD High DRH Switching Characteristics t ALE Pulse Width ALEW 1 t Address/Data 15–0 Setup Before ALE Deasserted ADAS t ALE Deasserted to Read Asserted ALERW t Delay Between RD Rising Edge to Next Falling Edge. ...
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... Preliminary Technical Data Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the ADSP-21365/6 is accessing external memory space. Table 22. 8-bit Memory Write Cycle Parameter Switching Characteristics: t ALE Pulse Width ALEW 1 t Address/Data 15–0 Setup Before ALE Deasserted ...
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... ADSP-21365/6 Table 23. 16-bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW 1 t Address/Data 15–0 Setup Before ALE Deasserted ADAS t ALE Deasserted to Write Asserted ALERW t Write Deasserted to ALE Asserted RWALE t Delay Between WR Rising Edge to next WR Falling Edge WRH 1 t Address/Data 15–0 Hold After ALE Deasserted ...
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... Referenced to drive edge. Serial port signals (SCLK, FS, data channel A,/data channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Rev. PrA | Page September 2004 ADSP-21365/6 Min Max Unit 2 ...
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... ADSP-21365/6 Table 26. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. Table 27. Serial Ports—External Late Frame Sync ...
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... HFSI SFSI DAI_P20-1 (FS) DAI_P20-1 (DATA CHANNEL A/B) DRIVE EDGE SCLK t DDTTE Figure 22. Serial Ports Rev. PrA | Page September 2004 ADSP-21365/6 DATA RECEIVE— EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKW t DFSE t t SFSE HOFSE t SDRE DATA TRANSMIT — EXTERNAL CLOCK ...
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... ADSP-21365/6 Input Data Port The timing requirements for the IDP are given in Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 28. IDP Parameter Timing Requirements ...
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... The timing requirements for the PDAP are provided in Table 29. PDAP is the parallel mode operation of channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2136x SHARC Processor Hardware Refer- Table 29. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements ...
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... ADSP-21365/6 Sample Rate Converter—Serial Input Port The SRC input signals (SCLK, FS, and SDATA) are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing spec- ifications provided in Table 30 are valid at the DAI_P20–1 pins. Table 30. SRC, Serial Input Port ...
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... SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the drive edge. Min 4 5.5 2 SAMPLE EDGE t SISCLKW t SIFS t SR CTDH t SRCTDD Figure 26. SRC Serial Output Port Timing Rev. PrA | Page September 2004 ADSP-21365/6 Max Unit SIHFS ...
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... ADSP-21365/6 SPDIF Transmitter Serial data input to the SPDIF transmitter can be formatted as 2 left justified right justified with word widths of 16, 18, 20 bits. The following sections provide timing for the transmitter. SPDIF Transmitter—Serial Input Waveforms Figure 27 shows the right-justified mode. LRCLK is HI for the left channel and LO for the right channel ...
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... TXCLK Frequency for TXCLK = 256 × FS Frame Rate Min 4 5 SAMPLE EDGE t SISCLKW t SISFS t SISD Figure 30. SPDIF Transmitter Input Timing Min Rev. PrA | Page September 2004 ADSP-21365/6 Max Unit SIHFS t SIH D Max Unit 147.5 MHz 98.4 MHz 73 ...
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... ADSP-21365/6 SPDIF Receiver The following sections describe timing as it relates to the SPDIF receiver. Internal Digital PLL Mode In internal Digital Phase-locked Loop mode the internal PLL (Digital PLL) generates the 512 × Fs clock. Table 34. SPDIF Receiver Internal Digital PLL Mode Timing Parameter ...
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... RIGHT-JUSTIFIED MODE ) MCP t DDS MSB t DDH t DDP t DDS MSB t DDH t DDP Figure 32. SPDIF Receiver External PLL Mode Timing Rev. PrA | Page September 2004 ADSP-21365/6 Min Max Unit 10 ns 100 MHz 1/2 SCLK Period ns 1/2 SCLK Period ns t DDS LSB ...
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... ADSP-21365/6 SPI Interface—Master The ADSP-21365/6 contains two SPI ports. The primary has dedicated pins and the secondary is available through the DAI. The timing provided in Table 36 and Table 37 on page 41 applies to both. Table 36. SPI Interface Protocol — Master Switching and Timing Specifications ...
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... LSB VALID LSB LSB VALID Figure 34. SPI Slave Timing Rev. PrA | Page September 2004 ADSP-21365/6 Min Max Unit 4 × PCLK 2 × PCLK 2 × t – PCLK ns 2 × ...
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... ADSP-21365/6 JTAG Test Access Port and Emulation Table 38. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP 1 t System Inputs Setup Before TCK Low ...
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... Preliminary Technical Data OUTPUT DRIVE CURRENTS Figure 36 shows typical I-V characteristics for the output driv- ers of the ADSP-21365/6. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, 125° -10 3.11V, 125° C ...
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... LOAD CAPACITANCE (pF) Figure 41. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The ADSP-21365/6 processor is rated for performance to a maximum junction temperature of 125°C. Table 39 through Table 42 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to- board measurement complies with JESD51-8 ...
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... Heatsink (INT–HS) LQFP (With heat slug soldered to PCB) Parameter Condition θ Airflow = 0 m/s JA θ Airflow = 1 m/s JMA θ Airflow = 2 m/s JMA θ JC Ψ Airflow = 0 m/s JT Ψ Airflow = 1 m/s JMT Ψ Airflow = 2 m/s JMT Typical Unit 16.50 °C/W 15.14 °C/W 14.35 °C/W 6.83 °C/W 0.129 °C/W 0.255 °C/W 0.261 °C/W Rev. PrA | Page September 2004 ADSP-21365/6 ...
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... ADSP-21365/6 136-BALL BGA PIN CONFIGURATIONS The following table shows the ADSP-21365/6’s pin names and their default function after reset (in parentheses). Table 43. 136-Ball Mini-BGA Pin Assignments Pin Name BGA Pin Name Pin# CLKCFG0 A01 CLKCFG1 XTAL A02 GND TMS A03 V DDEXT ...
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... K14 DAI_P14 (SFS23) P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 Rev. PrA | Page September 2004 ADSP-21365/6 BGA Pin Name BGA Pin# Pin# L01 AD0 M01 L02 WR M02 L04 GND M03 L05 GND M12 ...
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... ADSP-21365/6 Figure 42. 136-Ball Mini-BGA Pin Assignments (Bottom View, Summary KEY V A GND* DDINT VDD V A I/O SIGNALS DDEXT VSS *USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Rev. PrA | Page September 2004 ...
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... Preliminary Technical Data 144-LEAD LQFP PIN CONFIGURATIONS The following table shows the ADSP-21365/6’s pin names and their default function after reset (in parentheses). Table 44. 144-Lead LQFP Pin Assignments Pin Name LQFP Pin Name Pin No DDINT DDINT CLKCFG0 2 GND CLKCFG1 ...
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... ADSP-21365/6 PACKAGE DIMENSIONS The ADSP-21365/6 is available in a 136-ball Mini-BGA package and a 144-lead integrated heatsink LQFP package. 12.00 BSC SQ PIN A1 INDICATOR TOP VIEW 1.70 MAX 1. DIMENSIONS ARE IN MILIMETERS (MM). 2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0. ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. ...
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... NOT PROTRUDE BEYOND IT. ORDERING GUIDE Analog Devices offers a wide variety of audio algorithms and combinations to run on the ADSP-21365/6 processor. These products are sold as part of a chip set, bundled with necessary application software under special part numbers. For a complete list, visit our web site at www.analog.com/SHARC. ...
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... ADSP-21366SKSQ-ENG ADSP-21366SBBCZENG – ADSP-21366SBBC-ENG – ADSP-21366SBSQZENG – ADSP-21366SBSQ-ENG – ADSP-21366SCSQZENG –40 to 105 5 ADSP-21366SCSQ-ENG –40 to 105 1 Z indicates Lead Free package. For more information about lead free package offerings, please visit www.analog.com. 2 See Thermal Characteristics on page 44 for information on package thermal specifications ...
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... Preliminary Technical Data Rev. PrA | Page September 2004 ADSP-21365/6 ...
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... ADSP-21365/6 © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04625-0-10/04(PrA) Rev. PrA | Page September 2004 Preliminary Technical Data ...