XC5204 XILINX [Xilinx, Inc], XC5204 Datasheet - Page 43
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XC5204
Manufacturer Part Number
XC5204
Description
Field Programmable Gate Arrays
Manufacturer
XILINX [Xilinx, Inc]
Datasheet
1.XC5204.pdf
(73 pages)
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Configuration Switching Characteristics
Master Modes
Slave and Peripheral Modes
November 5, 1998 (Version 5.2)
Power-On-Reset
Program Latency
CCLK (output) Delay
Power-On-Reset
Program Latency
CCLK (input) Delay (required)
Note:
PROGRAM
period (slow)
period (fast)
period (required)
Vcc
INIT
X1532
At power-up, V
V
Description
Description
CC
R
is valid.
CC
must rise from 2.0 to V
CCLK OUTPUT or INPUT
T
POR
M0, M1, M2
(Required)
T
PI
Symbol
Symbol
T
T
T
T
T
T
T
CCLK
CCLK
CCLK
T
ICCK
T
ICCK
POR
POR
PI
PI
CC
min in less than 15 ms, otherwise delay configuration using PROGRAM until
T
XC5200 Series Field Programmable Gate Arrays
ICCK
VALID
Min
640
100
Min
100
40
2
6
2
6
5
3000
Max
Max
375
375
T
15
70
15
70
CCLK
DONE RESPONSE
I/ O
s per CLB column
s per CLB column
RE-PROGRAM
Units
Units
ms
ms
ns
ns
ns
s
s
<300 ns
<300 ns
>300 ns
7-125
7