MK60DN256ZVMD10 FREESCALE [Freescale Semiconductor, Inc], MK60DN256ZVMD10 Datasheet - Page 62

• Manufacturer Part Number: MK60DN256ZVMD10
• Description: K60 Sub-Family Data Sheet
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Peripheral operating requirements and behaviors
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
62
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
range the maximum frequency of operation is reduced.
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS10
DS11
DS12
DS13
DS14
DS15
Num
DS9
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Table 44. Master mode DSPI timing (full voltage range) (continued)
Operating voltage
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
Table 45. Slave mode DSPI timing (full voltage range)
Figure 24. DSPI classic SPI timing — master mode
K60 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
DS7
DS3
Description
First data
Description
DS8
First data
Table continues on the next page...
DS5
DS2
Data
Data
DS6
(t
(t
(t
BUS
BUS
SCK
4 x t
DS1
Last data
20.5
Min.
-4.5
—
4
4
0
/2) - 4
x 2) −
x 2) −
BUS
Last data
(t
SCK
8 x t
1.71
Min.
—
—
—
(t
0
2
7
/2) - 4
DS4
SCK/2)
BUS
Max.
10
—
—
—
—
—
—
+ 4
Freescale Semiconductor, Inc.
(t
SCK/2)
Max.
6.25
3.6
20
19
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
+ 4
MHz
Notes
Unit
ns
ns
ns
ns
ns
ns
ns
V
2
3