MK61FN1M0VMJ12 FREESCALE [Freescale Semiconductor, Inc], MK61FN1M0VMJ12 Datasheet - Page 24

• Manufacturer Part Number: MK61FN1M0VMJ12
• Description: K61 Sub-Family
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

General
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, IEEE 1588 timer, and I
24
Symbol
other module.
FB_CLK
Symbol
f
f
LPTMR
FLASH
f
f
SYS
BUS
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
Port rise and fall time (low drive strength)
Description
System and core clock
Bus clock
FlexBus clock
Flash clock
LPTMR clock
Description
• Slew disabled
• Slew enabled
• Slew disabled
• Slew enabled
• 1.71 ≤ V
• 2.7 ≤ V
• 1.71 ≤ V
• 2.7 ≤ V
• 1.71 ≤ V
• 2.7 ≤ V
• 1.71 ≤ V
• 2.7 ≤ V
Table 9. Device clock specifications (continued)
Table 10. General switching specifications
DD
DD
DD
DD
DD
DD
DD
DD
≤ 3.6V
≤ 3.6V
≤ 3.6V
≤ 3.6V
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
≤ 2.7V
≤ 2.7V
≤ 2.7V
≤ 2.7V
Table continues on the next page...
2
C signals.
Min.
100
100
1.5
16
—
—
—
—
—
—
—
—
Min.
2
—
—
—
—
—
Max.
Max.
14
36
24
14
36
24
—
—
—
—
—
0.5
8
8
4
4
4
4
Freescale Semiconductor, Inc.
Bus clock
Bus clock
cycles
cycles
Unit
MHz
MHz
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Notes
1,
3
3
3
4
5
2