CY8C20180_09 CYPRESS [Cypress Semiconductor], CY8C20180_09 Datasheet - Page 5

• Manufacturer Part Number: CY8C20180_09
• Description: CapSense Express-8 Configurable IOs
• Manufacturer: CYPRESS [Cypress Semiconductor]

The CapSense Analog System
The CapSense analog system contains the capacitive sensing
hardware. which supports CapSense Successive Approximation
(CSA) algorithm. This hardware performs capacitive sensing and
scanning without external components. Capacitive sensing is
configurable on each pin.
Additional System Resources
System resources provide additional capability useful to
complete systems. Additional resources are low voltage
detection and power on reset (POR).
■
■
An internal 1.8V reference provides a stable internal reference
so that capacitive sensing functionality is not affected by minor
V
Table 3. Examples of I
CapSense Express Software Tool
An easy to use software tool integrated with PSoC Express is
available for configuring and tuning CapSense Express devices.
Refer to the application note
Tool - AN42137”
Document Number: 001-17346 Rev. *F
DD
Slave Address
The I
over two wires.
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels and the advanced POR circuit elimi-
nates the need for a system supervisor.
changes.
Defined
2
127
127
C slave provides 50, 100, or 400 kHz communication
10
10
75
75
0
0
1
1
for details of the software tool.
B7
2
0
0
0
0
0
0
1
1
1
1
C Addressing
“CapSense™ Express Software
B6
0
0
0
0
0
0
0
0
1
1
B5
0
0
0
0
0
0
0
0
1
1
B4
0
0
0
0
1
1
1
1
1
1
I
The two modes of operation for the I
■
■
The I
locked to prevent accidental change by setting a flag in a config-
uration register.
I
I
first byte of a read or write transaction. The first byte of the trans-
action is used by the I
of the byte contains the R/W bit. If this bit is 0, the master
performs write operation to the addressed slave. If this bit is 1,
the master performs read operation from the addressed slave.
The LSB(B0) is eliminated when fixing the device address. For
example, if the slave address is 02h, then the required address
is 0000010 (7 bit) excluding LSB. If write operation is performed,
the LSB is 0 and the address is 00000100(04h). If read operation
is performed, the LSB is 1 and the address is 00000101(05h).
Table 3
CapSense Express Register Map
CapSense Express supports user configurable registers through
which the device functionality and parameters are configured.
For details, refer to the
2
2
2
B3
C device address is contained in the upper seven bits of the
Device register configuration and status read or write for
controller.
Command execution.
0
0
0
0
0
0
0
0
1
1
C Interface
C Device Addressing
2
C address is programmable during configuration. It can be
provides examples of I
B2
0
0
0
0
1
1
1
1
1
1
2
C master to address the slave. The LSB
CY8C201xx Register Reference
B1
0
0
1
1
0
0
1
1
1
1
2
C addressing.
0(W)
0(W)
0(W)
0(W)
0(W)
1(R)
1(R)
1(R)
1(R)
1(R)
B0
2
C interface are:
sent (in Hex) by
CY8C20180
Address to be
Master
FE
00
01
02
03
14
15
96
97
FF
Page 5 of 16
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