CY8C201A0_12 CYPRESS [Cypress Semiconductor], CY8C201A0_12 Datasheet
CY8C201A0_12
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CY8C201A0_12 Summary of contents
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CapSense ® Express™ Slider Capacitive Controllers Features Capacitive slider and button input ■ Choice of configurations: ❐ • 10-segment slider • 5-segment slider with remaining 5 pins configurable as ® CapSense or GPIO Robust sensing algorithm ❐ High sensitivity, low ...
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Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Pinouts .............................................................................. 4 Pin Definitions .................................................................. 4 Typical Circuits ................................................................. 5 I2C Interface ...................................................................... 7 I2C Device Addressing ................................................ 7 I2C Clock Stretching .................................................... 7 Format for Register Write and Read ........................... ...
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Pinouts Figure 1. 16-pin QFN (3 × 3 × 0.6 mm) (no e-pad) pinout – 5/10 Segment Slider Pin Definitions 16-pin QFN (no e-pad) – 5/10 Segment Slider Pin No. Name 1 GP0[0] Configurable as CapSense or GPIO ...
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Pinouts Figure 2. 16-pin SOIC (150 Mils) pinout – 5/10 Segment Slider Pin Definitions 16-pin SOIC – 5/10 Segment Slider Pin No. Name 1 GP0[3] Configurable as CapSense or GPIO 2 CSint Integrating Capacitor Input. The external capacitance is ...
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Typical Circuits Figure 3. Circuit 1 – Five-Segment Slider with Status LED and Two Buttons with Backlighting LEDs Figure 4. Circuit 2 – Compatibility with 1 Notes 4. 1.8 V VDD_I2C VDD_CE and 2.4 ...
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Typical Circuits (continued) Figure 5. Circuit 3 – Powering Down CapSense Express Device for Low Power Requirements Output enable Master Or Host Note 6. For low power requirements turned off, the concept mentioned in this ...
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I C Interface The CapSense Express devices support the industry standard I Configuring the device ■ Reading the status and data registers of the device ■ To control the device operation ■ Executing commands ■ 2 The I C ...
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Format for Register Write and Read Register write format Start Slave Addr + W A Reg Addr Register read format Start Slave Addr + W A Reg Addr Start Slave Addr + R A Data Legends Master A – ACK ...
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Operating Modes Commands Normal Mode In normal mode of operation, the acknowledgment time is optimized. The timings remain approximately the same for different configurations of the slave. acknowledgment times in normal 0x06–0x09, 0x0C, 0x0D, 0x10–0x17, 0x50, ...
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Registers Register Map Register Name Address (in Hex) INPUT_PORT0 00 INPUT_PORT1 01 STATUS_POR0 02 STATUS_POR1 03 OUTPUT_PORT0 04 OUTPUT_PORT1 05 CS_ENABL0 06 CS_ENABLE 07 GPIO_ENABLE0 08 GPIO_ENABLE1 09 INVERSION_MASK0 0A INVERSION_MASK1 0B INT_MASK0 0C INT_MASK1 0D STATUS_HOLD_MSK0 0E STATUS_HOLD_MSK1 0F ...
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Register Map (continued) Register Name Address (in Hex) OPR2_PRT0_01 24 OPR2_PRT1_01 25 OP_SEL_02 26 OPR1_PRT0_02 27 OPR1_PRT1_02 28 OPR2_PRT0_02 29 OPR2_PRT1_02 2A OP_SEL_03 2B OPR1_PRT0_03 2C OPR1_PRT1_03 2D OPR2_PRT0_03 2E OPR2_PRT1_03 2F OP_SEL_04 30 OPR1_PRT0_04 31 OPR1_PRT1_04 32 OPR2_PRT0_04 33 ...
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Register Map (continued) Register Name Address (in Hex) OPR2_PRT1_14 4D CS_NOISE_TH 4E CS_BL_UPD_TH 4F CS_SETL_TIME 50 CS_OTH_SET 51 CS_HYSTERISIS 52 CS_DEBOUNCE 53 CS_NEG_NOISE_TH 54 CS_LOW_BL_RST 55 CS_FILTERING 56 CS_SCAN_POS_00 57 CS_SCAN_POS_01 58 CS_SCAN_POS_02 59 CS_SCAN_POS_03 5A CS_SCAN_POS_04 5B CS_SCAN_POS_10 5C ...
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Register Map (continued) Register Name Address (in Hex) [12] 76 CS_SLID_MULM 77 CS_SLID_MULL 78 I2C_ADDR_LOCK 79 DEVICE_ID 7A DEVICE_STATUS 7B I2C_ADDR_DM 7C [13] 7D SLEEP_PIN 7E SLEEP_CTRL 7F SLEEP_SA_CNTR 80 CS_READ_BUTTON 81 CS_READ_BLM 82 CS_READ_BLL 83 CS_READ_DIFFM 84 CS_READ_DIFFL 85 ...
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CapSense Express Commands [14] Command Description Get firmware revision Store current configuration to NVM Restore factory configuration Write NVM POR defaults ...
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Layout Guidelines and Best Practices CapSense Button Shapes Button Layout Design X: Button to ground clearance (Refer to Y: Button to button clearance (Refer to Recommended via Hole Placement Document Number: 001-54607 Rev. *G Table 2 on page ...
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Slider Shapes Dimensions for Slider Design [15] Parameter Width of the Segment (A) Clearance between Segments (B) Height of the segment (C) Note 15. The end segments of sliders should be grounded. Document Number: 001-54607 Rev. *G Min Max Recommended ...
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Table 2. Layout Guidelines and Best Practices S. No. Category 1 Button shape 2 Button size 3 Button-button spacing 4 Button ground clearance 5 Slider segment pattern Saw tooth pattern 6 Number of slider segments 7 Slider segment size 8 ...
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The Recommended maximum overlay thickness (with external CSInt (without external CSInt). For more details refer to the section “The Integrating Capacitor (Cint)” in AN53490. Example PCB Layout Design with 5 Segment Slider, 2 Buttons with ...
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Operating Voltages 2 For details Ack time, refer to times the values mentioned in these tables. CapSense Constraints Parameter Parasitic capacitance ( the CapSense P sensor Supply voltage variation ( Document Number: ...
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Absolute Maximum Ratings Parameter Description T Storage temperature STG T Bake temperature BAKETEMP t Bake time BAKETIME T Ambient temperature with power A applied V Supply voltage voltage on CapSense inputs IO ...
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Electrical Specifications DC Electrical Specifications DC Chip-Level Specifications Table 3. DC Chip-Level Specifications Parameter Description V Supply voltage DD I Supply current DD I Deep sleep mode current with SB POR and LVD active I Deep sleep mode current with ...
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Table 4. 5-V and 3.3-V DC GPIO Specifications (continued) Parameter Description C Capacitive load on pins as input IN C Capacitive load on pins as output OUT This table lists guaranteed maximum and minimum specifications for the voltage and temperature ...
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DC POR Specifications Table 6. DC POR Specifications Parameter Description V Value for PPOR Trip 2.7 V PPOR0 3 PPOR1 DD VLVD0 V Value for LVD Trip DD VLVD2 ...
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CapSense Electrical Characteristics Max (V) Typ (V) Min (V) 3.6 3.3 3.1 2.90 2.7 2.45 5.25 5.0 4.75 AC Electrical Specifications AC Chip-Level Specifications Table 9. 5-V and 3.3-V AC Chip-Level Specifications Parameter Description F Internal low-speed oscillator 32K1 (ILO) ...
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AC GPIO Specifications Table 11. 5-V and 3.3-V AC GPIO Specifications Parameter Description t Rise time, strong mode, Rise0 Cload = 50 pF, Port 0 t Rise time, strong mode, Rise1 Cload = 50 pF, Port 1 t Fall time, ...
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Figure 10. Definition of Timing for Fast/Standard Mode on the I I2C_SDA T SUDATI2C T HDSTAI2C I2C_SCL T T HIGHI2C LOWI2C S START Condition Document Number: 001-54607 Rev SUSTAI2C HDDATI2C Sr Repeated START Condition CY8C201A0 C Bus ...
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Appendix 2 Examples of Frequently Used I C Commands S. No. Requirement 1 Enter into setup mode 2 Enter into normal mode 3 Load factory defaults to RAM registers software reset 5 Save current configuration to flash ...
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Ordering Information Package Ordering Code Diagram CY8C201A0-LDX2I 001-09116 CY8C201A0-SX2I 51-85068 Ordering Code Definitions 201 Thermal Impedances Table 14. Thermal Impedances by Package Package 16-pin QFN[1] 16-pin SOIC Solder Reflow Specifications Table 15. Solder Reflow ...
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Package Diagrams Figure 11. 16-pin Chip On Lead (3 × 3 × 0.6 mm) LG16A/LD16A (Sawn) Package Outline, 001-09116 Document Number: 001-54607 Rev. *G CY8C201A0 001-09116 *F Page ...
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Package Diagrams (continued) Figure 12. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068 Document Number: 001-54607 Rev. *G CY8C201A0 51-85068 *D Page ...
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Acronyms Table 16 lists the acronyms that are used in this document. Table 16. Acronyms Used in this Datasheet Acronym Description AC alternating current CMOS complementary metal oxide semiconductor DC direct current EEPROM electrically erasable programmable read-only memory EMC electromagnetic ...
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Glossary active high 1. A logic signal having its asserted state as the logic 1 state logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. ...
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Glossary (continued) configuration In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. space crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric ...
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Glossary (continued) interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service A block ...
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Glossary (continued) PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A ...
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Glossary (continued name for a power net meaning "voltage drain." The most positive power supply signal. Usually 3 name for a power net meaning "voltage source." The most negative power supply ...
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Document History Page Document Title: CY8C201A0, CapSense Document Number: 001-54607 Orig. of Rev. ECN Change ** 2741726 SLAN / FSU *A 2821828 SSHH / FSU *B 2892629 NJF *C 3043236 ARVM *D 3085081 NJF *E 3276234 ARVM *F 3390450 SLAN ...
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