Z86E3016ESE ZILOG [Zilog, Inc.], Z86E3016ESE Datasheet
Z86E3016ESE
Related parts for Z86E3016ESE
Z86E3016ESE Summary of contents
Page 1
FEATURES ROM RAM* Device (KB) (Bytes) Z86E30 4 237 Z86E31 2 125 Z86E40 4 236 Note: *General-Purpose Standard Temperature (V = 3.5V to 5.5V) CC Extended Temperature (V = 4.5V to 5.5V) CC Available Packages: 28-Pin DIP/SOIC/PLCC OTP (Z86E30/31 only) ...
Page 2
Z86E30/E31/E40 Z8 4K OTP Microcontroller allel I/O with or without handshake, and address/data bus for interfacing external memory. Notes: All Signals with a preceding front slash, "/", are active Low, for example, B//W (WORD is active Low); /B/W (BYTE is ...
Page 3
Zilog AD 11 MCU MSN Port Port 0 PGM + T est Mode Logic EPM /PGM P32 P30 /CE XT1 Figure 2. EPROM Programming Block Diagram DS97Z8X0500 11- 0 ...
Page 4
Z86E30/E31/E40 Z8 4K OTP Microcontroller PIN IDENTIFICATION R//W 1 P25 P26 P27 P04 P05 P06 P14 P15 40-Pin DIP P07 VCC P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 20 /AS Figure 3. 40-Pin DIP Pin Configuration* Standard Mode 4 ...
Page 5
Zilog R//W Table 2. 44-Pin PLCC Pin Identification Pin # Symbol Function 1-2 GND Ground 3-4 P12-P13 Port 1, Pins 2,3 In/Output 5 P03 Port 0, Pin 3 6-10 P20-P24 Port 2, Pins 0,1,2,3,4 11 /DS Data Strobe 12 NC ...
Page 6
Z86E30/E31/E40 Z8 4K OTP Microcontroller R//W Table 3. 44-Pin QFP Pin Identification Pin # Symbol Function 1-2 P05-P06 Port 0, Pins 5,6 3-4 P14-P15 Port 1, Pins 4,5 5 P07 Port 0, Pin 7 6-7 VCC Power Supply 8-9 P16-P17 ...
Page 7
Zilog 40-Pin DIP A7 VCC /CE /OE EPM VPP Figure 6. 40-Pin DIP Pin Configuration* EPROM Mode DS97Z8X0500 Table 4. 40-Pin DIP Package Pin ...
Page 8
Z86E30/E31/E40 Z8 4K OTP Microcontroller Table 5. 44-Pin PLCC Pin Configuration EPROM Programming Mode Pin # Symbol Function 1-2 GND Ground 3 Connection 5 A3 Address 3 6-10 D0-D4 Data 0,1,2,3,4 11- Connection 14-16 D5-D7 Data ...
Page 9
Zilog Table 6. 44-Pin QFP Pin Identification EPROM Programming Mode Pin # Symbol Function 1-2 A5-A6 Address 5,6 3 Connection 5 A7 Address 7 6-7 V Power Supply CC 8- Connection 11 /CE Chip Select 12 ...
Page 10
Z86E30/E31/E40 Z8 4K OTP Microcontroller 1 P25 P26 P27 P04 P05 P06 P07 28-Pin DIP VCC XTAL2 XTAL1 P31 P32 P33 14 P34 Figure 9. Standard Mode 28-Pin DIP/SOIC Pin Configuration* Table 7. 28-Pin DIP/SOIC/PLCC Pin Identification* Pin # Symbol ...
Page 11
Zilog XXX A5 XXX A6 XXX A7 28-Pin PLCC VCC XXX XXX NC XXX /CE 11 XXX /OE 12 Figure 12. EPROM Programming Mode 28-Pin PLCC Pin Configuration DS97Z8X0500 Pin # Symbol 1-3 D5-D7 4-7 A4-A7 26 ...
Page 12
Z86E30/E31/E40 Z8 4K OTP Microcontroller ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to V Voltage on V Pin with Respect Voltage on XTAL1 and /RESET Pins with Respect ...
Page 13
Zilog CAPACITANCE GND = 0V 1.0 MHz; unmeasured pins returned to GND Parameter Min Input capacitance 0 Output capacitance 0 I/O capacitance 0 DC ELECTRICAL CHARACTERISTICS Sym Parameter Note [3] ...
Page 14
Z86E30/E31/E40 Z8 4K OTP Microcontroller Sym Parameter Note [3] I Supply Current CC I Standby Current CC1 Halt Mode I Standby Current CC2 Stop Mode I Auto Latch ALL Low Current I Auto Latch ALH High Current T Power On ...
Page 15
Zilog V Sym Parameter Note [3] V Clock Input High 4.5V CH Voltage 5.5V V Clock Input Low 4.5V CL Voltage 5.5V V Input High Voltage 4.5V IH 5.5V V Input Low Voltage 4.5V IL 5.5V V Output High 4.5V ...
Page 16
Z86E30/E31/E40 Z8 4K OTP Microcontroller V Sym Parameter Note [3] I Auto Latch High 4.5V ALH Current 5.5V T Power On Reset 4.5V POR 5.5V V Auto Reset Voltage LV 1. Device does not function down to the Auto Reset ...
Page 17
Zilog R//W , /DM 12 Port 0 18 Port 1 1 /AS 4 /DS (Read) Port1 /DS (W rite) Figure 14. External I/O or Memory Read/Write Timing DS97Z8X0500 ...
Page 18
Z86E30/E31/E40 Z8 4K OTP Microcontroller No Symbol Parameter 1 TdA(AS) Address Valid to /AS Rise Delay 2 TdAS(A) /AS Rise to Address Float Delay 3 TdAS(DR) /AS Rise to Read Data Req’d Valid 4 TwAS /AS Low Width 5 TdAS(DS) ...
Page 19
Zilog No Symbol Parameter 1 TdA(AS) Address Valid to /AS Rise Delay 2 TdAS(A) /AS Rise to Address Float Delay 3 TdAS(DR) /AS Rise to Read Data Req’d Valid 4 TwAS /AS Low Width 5 TdAS(DS) Address Float to /DS ...
Page 20
Z86E30/E31/E40 Z8 4K OTP Microcontroller Clock TIN 4 IRQN 8 Clock Setup Stop Mode Recovery Source Figure 15. Additional Timing Diagram ...
Page 21
Zilog Additional Timing Table (Divide-By-One Mode) No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 ...
Page 22
Z86E30/E31/E40 Z8 4K OTP Microcontroller Handshake Timing Diagrams Data In Valid Data In 1 /DAV (Input) RDY (Output) Data Out 7 /DAV (Output) RDY (Input Delayed DAV 4 Figure 16. Input Handshake Timing Data Out Valid 8 ...
Page 23
Zilog Additional Timing Table No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer ...
Page 24
Z86E30/E31/E40 Z8 4K OTP Microcontroller PIN FUNCTIONS EPROM Programming Mode D7-D0 Data Bus. The data can be read from or written to external memory through the data bus. A11-A0 Address Bus. During programming, the EPROM address is written to the ...
Page 25
Zilog Port 0 (P07-P00). Port 8-bit, bidirectional, CMOS- compatible I/O port. These eight I/O lines can be config- ured under software control as a nibble I/O port address port for interfacing external memory. The ...
Page 26
Z86E30/E31/E40 Z8 4K OTP Microcontroller Open-Drain OEN Out 1 Port 0 (I/O) 4 Handshake Controls /DAV0 and RDY0 (P32 and P35) 2.3V Hysteresis R 500 k Figure 18. Port 0 Configuration ...
Page 27
Zilog Port 1 (P17-P10). Port 8-bit, bidirectional, CMOS- compatible port with multiplexed Address (A7-A0) and Data (D7-D0) ports. These eight I/O lines can be pro- grammed as inputs or outputs or can be configured under software control ...
Page 28
Z86E30/E31/E40 Z8 4K OTP Microcontroller Port 2 (P27-P20). Port 8-bit, bidirectional, CMOS- compatible I/O port. These eight I/O lines can be config- ured under software control as an input or output, indepen- dently. All input buffers are ...
Page 29
Zilog Port 3 (P37-P30). Port 8-bit, CMOS-compatible port with four fixed inputs (P33-P30) and four fixed outputs (P37-P34). These eight lines can be configured by soft- ware for interrupt and handshake control functions. Port 3, Pin 0 ...
Page 30
Z86E30/E31/E40 Z8 4K OTP Microcontroller Z86E40 MCU P30 P31 (AN1 P32 (AN2) + P33 (REF) - From Stop Mode Recovery Source 30 Port 3 (I/O or Control) Auto Latch R 500 K R247 = P3M 1 = Analog ...
Page 31
Zilog Pin I/O CTC1 P30 IN P31 P32 IN P33 IN P34 OUT P35 OUT P36 OUT T OUT P37 OUT Comparator Inputs. Port 3, P31, and P32, each have a comparator front end. The comparator reference ...
Page 32
Z86E30/E31/E40 Z8 4K OTP Microcontroller FUNCTIONAL DESCRIPTION The MCU incorporates the following special functions to enhance the standard Z8 architecture to provide the user with increased design flexibility. RESET. The device is reset in one of three ways: 1. Power-On ...
Page 33
Zilog EPROM Protect. When in ROM Protect Mode, and exe- cuting out of External Program Memory, instructions LDC, LDCI, LDE, and LDEI cannot read Internal Program Mem- ory. When in ROM Protect Mode and executing out of Internal Program Memory, ...
Page 34
Z86E30/E31/E40 Z8 4K OTP Microcontroller Expanded Register File (ERF). The register file has been expanded to allow for additional system control registers, mapping of additional peripheral devices and input/output ports into the register address area. The Z8 register ad- dress ...
Page 35
Zilog The upper nibble of the register file address provided by the register pointer specifies the active working-register group ...
Page 36
Z86E30/E31/E40 Z8 4K OTP Microcontroller REGISTER POINTER Working Register Expanded Register Group Pointer Group Pointer Z8 Reg. File %FF %FO Z86E30/E40 Only Z86E30/E40 Only %7F %0F %00 Notes Unknown † ...
Page 37
Zilog General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the V voltage-specified operating range. The CC register R254 is ...
Page 38
Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog DS97Z8X0500 ...
Page 39
Zilog The counters can be programmed to start, stop, restart to continue, or restart from the initial value. The counters can also be programmed to stop upon reaching zero (single pass mode automatically reload the initial value and ...
Page 40
Z86E30/E31/E40 Z8 4K OTP Microcontroller Interrupts. The MCU has six different interrupts from six different sources. The interrupts are maskable and priori- tized (Figure 28). The six sources are divided as follows: four sources are claimed by Port 3 lines ...
Page 41
Zilog When more than one interrupt is pending, priorities are re- solved by a programmable priority encoder that is con- trolled by the Interrupt Priority Register (IPR). An interrupt machine cycle is activated when an interrupt request is granted. Thus, ...
Page 42
Z86E30/E31/E40 Z8 4K OTP Microcontroller Power-On Reset (POR). A timer circuit clocked by a ded- icated on-board RC oscillator is used for the Power-On Re- set (POR) timer function. The POR timer allows V the oscillator circuit to stabilize before ...
Page 43
Zilog PCON (FH) 00H Default Setting After Reset Comparator Output Port 3 (D0). Bit 0 controls the com- parator output in Port 3. A "1" in this location brings the comparator ...
Page 44
Z86E30/E31/E40 Z8 4K OTP Microcontroller mode will reduce the drive of the oscillator (OSC). The de- fault value is 1. Note: 4 MHz is the maximum external clock frequency when running in the low EMI oscillator mode. STOP-Mode Recovery Register ...
Page 45
Zilog SCLK/TCLK Divide-by-16 Select (D0). This bit of the SMR controls a divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources ...
Page 46
Z86E30/E31/E40 Z8 4K OTP Microcontroller Table 12. STOP-Mode Recovery Source SMR Source selection POR recovery only P30 transition P31 transition (Not in analog mode P32 ...
Page 47
Zilog (Figures 33 and 34). After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR ( Default setting after RESET DS97Z8X0500 WDTMR cannot be ...
Page 48
Z86E30/E31/E40 Z8 4K OTP Microcontroller /Reset 4 Clock Filter WDT Select (WDTMR) CLK Source Select (WDTMR) XTAL Internal RC OSC. 2V Operating Voltage Det. + VDD VLV - /WDT From Stop Mode Recovery Source Stop Delay Select (SMR) Auto Reset ...
Page 49
Zilog 3.7 VCC (Volts) 3.5 3.3 3.1 2.9 2.7 2.5 2.3 -60 -40 Figure 35. Typical Z86E40 V DS97Z8X0500 - Voltage vs Temperature Z86E30/E31/E40 ...
Page 50
Z86E30/E31/E40 Z8 4K OTP Microcontroller EPROM MODE. Table 14 shows the programming voltages of each pro- gramming mode. Table 15, Figures 38, 39, and 40 show the programming timing of each programming mode. Fig- ure 41 shows the circuit diagram ...
Page 51
Zilog Parameters Name 1 Address Setup Time 2 Data Setup Time 3 V Setup Setup Time CC 5 Chip Enable Setup Time 6 Program Pulse Width 7 Data Hold Time 8 /OE Setup Time 9 Data Access ...
Page 52
Z86E30/E31/E40 Z8 4K OTP Microcontroller VIH Address VIL VIH Data Invalid VIL VH VPP VIL VH EPM VIL VCC 4.5V VIH /CE VIL VIH /OE VIL VIH /PGM VIL 3 Figure 36. EPROM Read Mode Timing Diagram 52 Address Stable ...
Page 53
Zilog Z86E40 TIMING DIAGRAMS V IH Address Data EPM VCC ...
Page 54
Z86E30/E31/E40 Z8 4K OTP Microcontroller P20 P10 36 D1 P21 P11 D2 37 P22 P12 D3 38 P23 P13 D4 39 P24 P14 D5 2 P25 P15 D6 3 P26 P16 D7 4 P27 P17 A0 26 ...
Page 55
Zilog P20 25 D1 P21 D2 26 P22 D3 27 P23 D4 28 P24 D5 1 P25 D6 2 P26 D7 3 P27 A0 19 P30 P00 A1 20 P31 P01 A2 21 P32 P02 A3 23 ...
Page 56
Z86E30/E31/E40 Z8 4K OTP Microcontroller Note ensure proper operaton, Zilog recommends Vcc range of the device Vcc specification, But Vcc = 5.0V is acceptable. 56 Start Addr = First Location Vcc = 6.0V Vpp = 12. ...
Page 57
Zilog EXPANDED REGISTER FILE CONTROL REGISTERS PCON (FH) 00H Default Setting After Reset † Must Be 1 for Z86E30/E31 Figure 41. Port Configuration Register Write Only SMR (FH ...
Page 58
Z86E30/E31/E40 Z8 4K OTP Microcontroller Z8 CONTROL REGISTER DIAGRAMS R240 Figure 45. Reserved R241 TMR Default After Reset = 00H Figure 46. Timer Mode ...
Page 59
Zilog R246 P2M Default After Reset Figure 51. Port 2 Mode Register F6H: Write Only R247 P3M Default After Reset = 00H † ...
Page 60
Z86E30/E31/E40 Z8 4K OTP Microcontroller R250 IRQ Default After Reset = 00H Figure 55. Interrupt Request Register FAH: Read/Write R251 IMR † This option ...
Page 61
Zilog PACKAGE INFORMATION DS97Z8X0500 Figure 61. 40-Pin DIP Package Diagram Figure 62. 44-Pin PLCC Package Diagram Z86E30/E31/E40 Z8 4K OTP Microcontroller 1 61 ...
Page 62
Z86E30/E31/E40 Z8 4K OTP Microcontroller Figure 64. 40-Pin Cerdip Window Lid Package Diagram 62 Figure 63. 44-Pin QFP Package Diagram Zilog DS97Z8X0500 ...
Page 63
Zilog Figure 66. 28-Pin Window Cerdip Package Diagram DS97Z8X0500 Figure 65. 28-Pin DIP Package Diagram Z86E30/E31/E40 Z8 4K OTP Microcontroller 1 63 ...
Page 64
Z86E30/E31/E40 Z8 4K OTP Microcontroller 64 Figure 67. 18-Pin SOIC Package Diagram Zilog DS97Z8X0500 ...
Page 65
... PLCC Z86E4016PSC Z86E4016VSC Z86E4016PEC Z86E4016VEC Z86E30 (16 MHz) 28-Pin Cerdip 28-Pin DIP Window Lid Z86E3016PSC Z86E3016ESE Z96E3016PEC Z86E3016SSC Z86E3016SEC Z86E31 (16 MHz) 28-Pin DIP 28-Pin Cerdip Window Lid Z86E3116PSC Z86E3116SSC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. ...
Page 66
Z86E30/E31/E40 Z8 4K OTP Microcontroller © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information ...