PIC12F1516 MICROCHIP [Microchip Technology], PIC12F1516 Datasheet - Page 198

• Manufacturer Part Number: PIC12F1516
• Description: 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC16(L)F1516/7/8/9
21.4
All MSSP I
shifted out MSb first. Six SFR registers and 2 interrupt
flags interface the module with the PIC
troller and user software. Two pins, SDA and SCL, are
exercised by the module to communicate with other
external I
21.4.1
All communication in I
byte is sent from a master to a slave or vice-versa, fol-
lowed by an Acknowledge bit sent back. After the 8th
falling edge of the SCL line, the device outputting data
on the SDA changes that pin to an input and reads in
an Acknowledge value on the next clock pulse.
The clock signal, SCL, is provided by the master. Data
is valid to change while the SCL signal is low, and
sampled on the rising edge of the clock. Changes on
the SDA line while the SCL line is high define special
conditions on the bus, explained below.
21.4.2
There is language and terminology in the description
of I
I
used in the rest of this document without explanation.
This table was adapted from the Philips I
specification.
21.4.3
Selection of any I
forces the SCL and SDA pins to be open-drain. These
pins should be set by the user to inputs by setting the
appropriate TRIS bits.
21.4.4
The hold time of the SDA pin is selected by the SDAHT
bit of the SSPCON3 register. Hold time is the time SDA
is held valid after the falling edge of SCL. Setting the
SDAHT bit selects a longer 300 ns minimum hold time
and may help on buses with large capacitance.
DS41452B-page 198
2
C. That word usage is defined below and may be
Note: Data is tied to output zero when an I
2
C communication that have definitions specific to
I
BYTE FORMAT
DEFINITION OF I
SDA AND SCL PINS
SDA HOLD TIME
2
2
mode is enabled.
C devices.
C
2
C communication is byte oriented and
MODE OPERATION
2
C mode with the SSPEN bit set,
2
C is done in 9-bit segments. A
2
C TERMINOLOGY
®
microcon-
Preliminary
2
2
C
C
TABLE 21-2:
Transmitter
Receiver
Master
Slave
Multi-master
Arbitration
Synchronization Procedure to synchronize the
Idle
Active
Addressed
Slave
Matching
Address
Write Request
Read Request
Clock Stretching When a device on the bus hold
Bus Collision
TERM
I
2
The device which shifts data in
Master sends an address byte with
The device which shifts data out
onto the bus.
from the bus.
The device that initiates a transfer,
generates clock signals and termi-
nates a transfer.
The device addressed by the mas-
ter.
A bus with more than one device
that can initiate data transfers.
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
clocks of two or more devices on
the bus.
No master is controlling the bus,
and both SDA and SCL lines are
high.
Any time one or more master
devices are controlling the bus.
Slave device that has received a
matching address and is actively
being clocked by a master.
Address byte that is clocked into a
slave that matches the value
stored in SSPADD.
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
SCL low to stall communication.
Any time the SDA line is sampled
low by the module while it is out-
putting and expected high state.
C BUS TERMS
 2011 Microchip Technology Inc.
Description