PIC12F1516 MICROCHIP [Microchip Technology], PIC12F1516 Datasheet - Page 216
PIC12F1516
Manufacturer Part Number
PIC12F1516
Description
28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC12F1516.pdf
(344 pages)
- Current page: 216 of 344
- Download datasheet (4Mb)
PIC16(L)F1516/7/8/9
21.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in the SSPCON1 register and
by setting the SSPEN bit. In Master mode, the SDA and
SCK pins must be configured as inputs. The MSSP
peripheral hardware will override the output driver TRIS
controls when necessary to drive the pins low.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I
bus is Idle.
In Firmware Controlled Master mode, user code
conducts all I
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDA and SCL lines.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
• Start condition detected
• Stop condition detected
• Data transfer byte transmitted/received
• Acknowledge transmitted/received
• Repeated Start generated
DS41452B-page 216
Note 1: The MSSP module, when configured in
2
C bus may be taken when the P bit is set, or the
I
2: When in Master mode, Start/Stop detec-
2
C MASTER MODE
I
ing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the SSP-
BUF will not be written to and the WCOL
bit will be set, indicating that a write to the
SSPBUF did not occur
tion is masked and an interrupt is gener-
ated when the SEN/PEN bit is cleared and
the generation is complete.
2
C Master mode, does not allow queue-
2
C bus operations based on Start and
Preliminary
21.6.1
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. Start and Stop conditions indicate the beginning
and end of transmission.
A Baud Rate Generator is used to set the clock fre-
quency output on SCL. See
Generator”
I
2
C MASTER MODE OPERATION
for more detail.
2011 Microchip Technology Inc.
Section 21.7 “Baud Rate
2
C bus will
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