MC68HC05K1 FREESCALE [Freescale Semiconductor, Inc], MC68HC05K1 Datasheet - Page 45

• Manufacturer Part Number: MC68HC05K1
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

4.3.2.1 IRQ/V
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
NOTE:
PP
Pin
An interrupt signal on the IRQ/V
request. The IRQ/V
its input to improve noise immunity. After completing the current
instruction, the CPU tests these bits:
If both the IRQF bit and the IRQE bit are set, and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQF bit
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request.
external interrupts.
The IRQ/V
low-level triggered, depending on the mask option selected.
When the edge- and level-sensitive trigger mask option is selected:
When the edge-sensitive only trigger mask option is selected:
If the IRQ/V
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IRQF bit in the interrupt status and control register
IRQE bit in the interrupt status and control register
I bit in the condition code register
A falling edge or a low level on the IRQ/V
interrupt request.
As long as the IRQ/V
present, and the CPU continues to execute the interrupt service
routine. The edge- and level-sensitive trigger option allows
connection to the IRQ/V
sources.
A falling edge of the IRQ/V
request.
A subsequent interrupt request can be latched only after the
voltage level on the IRQ/V
again to logic 0.
PP
PP
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pin is negative-edge triggered only or negative-edge and
pin is not in use, connect it to the V
PP
Interrupts
pin contains an internal Schmitt trigger as part of
PP
pin is low, an external interrupt request is
PP
PP
PP
PP
pin to multiple wired-OR interrupt
pin latches an external interrupt
pin returns to logic 1 and then falls
pin latches an external interrupt
Figure 4-1
PP
shows the logic for
pin latches an external
DD
pin.
Interrupt Types
Technical Data
Interrupts