CY8C5246LTI-029 CYPRESS [Cypress Semiconductor], CY8C5246LTI-029 Datasheet
CY8C5246LTI-029
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CY8C5246LTI-029 Summary of contents
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General Description With its unique array of configurable blocks, PSoC analog, and digital peripheral functions in a single chip. The CY8C52 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high ...
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Contents 1. Architectural Overview ....................................................3 2. Pinouts ..............................................................................5 3. Pin Descriptions ...............................................................8 4. CPU ....................................................................................9 4.1 ARM Cortex-M3 CPU ................................................9 4.2 Cache Controller .....................................................11 4.3 DMA and PHUB ......................................................11 4.4 Interrupt Controller ..................................................14 5. Memory ............................................................................16 5.1 Static RAM ..............................................................16 ...
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Architectural Overview Introducing the CY8C52 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C52 family provides configurable blocks of analog, digital, and interconnect circuitry ...
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In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the CY8C52 family these blocks can include four 16-bit timers, 2 counters, and PWM blocks slave, master, and ...
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PSoC uses a JTAG (4 wire) or SWD (2 wire) interface for programming, debug, and test. Using these standard interfaces enables the designer to debug or program the PSoC with a variety of hardware solutions from Cypress or third party ...
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GPIO) P2[5] 1 (TRACEDATA[2], GPIO) P2[6] 2 (TRACEDATA[3], GPIO) P2[7] 3 (I2C0: SCL, SIO) P12[4] 4 (I2C0: SDA, SIO) P12[5] 5 (GPIO) P6[4] 6 (GPIO) P6[5] 7 (GPIO) P6[6] 8 (GPIO) P6[7] 9 Vssb 10 Ind 11 Vboost 12 ...
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Figure 2-3. Example Schematic for 100-pin TQFP Part with Power Connections Vddd C6 0.1 uF Vssd 1 P2[5] 2 P2[6] 3 P2[7] 4 P12[4], SIO 5 P12[5], SIO 6 P6[4] 7 P6[5] 8 P6[6] 9 P6[7] 10 Vssb 11 Ind ...
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Figure 2-4. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance Vssd Plane 3. Pin Descriptions IDAC0. Low resistance output pin for high IDAC. Extref0, Extref1. External reference input to the analog system. GPIO. General purpose I/O pin ...
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V . Supply for all digital peripherals and digital core regulator. DDD V must be less than or equal to V DDD DDA V . Ground for all analog peripherals. SSA V . Ground connection for boost pump. SSB V ...
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The Thumb -2 instruction set, which offers ARM-level performance at Thumb-level code density. This includes 16-bit and 32-bit instructions. Advanced instructions include: Bit-field control Hardware multiply and divide Saturation If-Then Wait for events and interrupts Exclusive access and barrier ...
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Table 4-2. Cortex M3 CPU Registers (continued) Register Description CONTROL A 2-bit register for controlling the operating mode. Bit privileged level in thread mode user level in thread mode. Bit default stack ...
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Priority Levels The CPU always has higher priority than the DMA controller when their accesses require the same bus resources. Due to the system architecture, the CPU can never starve the DMA. DMA channels of higher priority (lower priority ...
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Scatter Gather DMA In the case of scatter gather DMA, there are multiple noncontiguous sources or destinations that are required to effectively carry out an overall DMA transaction. For example, a packet may need to be transmitted off of ...
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Interrupt Controller The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table 4-5. Cortex-M3 Exceptions and Interrupts Exception Exception Type Number 1 Reset –3 (highest) 2 NMI –2 3 Hard fault –1 4 ...
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Table 4-6. Interrupt Vector Table (continued) Interrupt # Cortex-M3 Exception # ...
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Memory 5.1 Static RAM CY8C52 Static RAM (SRAM) is used for temporary data storage. Code can be executed at full speed from the portion of SRAM that is located in the code space. This process is slower from SRAM ...
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Memory Map The Cortex-M3 has a fixed address map, which allows peripherals to be accessed by simple memory access instructions. 5.5.1 Address Map The 4-GB address space is divided into the ranges shown in Table 5-2: Table 5-2. Address ...
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System Integration 6.1 Clocking System The clocking system generates, divides, and distributes clocks throughout the PSoC system. For the majority of systems, no external crystal is required. The IMO and PLL together can generate MHz ...
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MHz 4-25 MHz IMO ECO 12-48 MHz Doubler Digital Clock Divider 16 bit Digital Clock Divider 16 bit 7 Digital Clock Divider 16 bit Digital Clock Divider 16 bit 6.1.1 Internal Oscillators 6.1.1.1 Internal Main Oscillator In most designs ...
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The central timewheel can be programmed to wake the system periodically and optionally issue an interrupt. This enables flexible, periodic wakeups from low power modes or coarse timing applications. Systems that require accurate timing should use the RTC capability instead ...
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Four 16-bit clock dividers generate clocks for the analog system components that require clocking, such as the ADC. The analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. This ...
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Power Modes PSoC 5 devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing ...
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Figure 6-5. Power Mode Transitions Active Manual Sleep Alternate Active 6.2.1.1 Active Mode Active mode is the primary operating mode of the device. When in active mode, the active configuration template bits control which available resources are enabled or disabled. ...
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The boost converter can be operated in two different modes: active and standby. Active mode is the normal mode of operation where the boost regulator actively generates a regulated output voltage. In standby mode, most boost functions are disabled, thus ...
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ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt circuits are available to detect when V go outside a voltage range. For AHVI, V fixed trip level. For ALVI and DLVI, V DDA compared to trip ...
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Digital Input Path PRT[x]CTL PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Analog Capsense Global Control CAPS[x]CFG1 PRT[x]AG Analog Global Enable ...
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Digital Input Path PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Digital Input Path ...
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Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts ...
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Resistive Pull Up or Resistive Pull Down Resistive pull up or pull down, respectively, provides a series resistance in one of the data states and strong drive in the other. Pins can be used for digital input and output in ...
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Adjustable Output Level This section applies only to SIO pins. SIO port pins support the ability to provide a regulated high output level for interface to external signals that are lower in voltage than the SIO’s respective V . ...
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Special Pin Functionality Some pins on the device include additional special functionality in addition to their GPIO or SIO functionality. The specific special function pins are listed in “Pinouts” on page 5. The special features are: Digital 4 to ...
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Example Analog Components The following is a sample of the analog components available in PSoC Creator for the CY8C52 family. The exact amount of hardware resources (SC/CT blocks, routing, RAM, flash) used by a component varies with the features ...
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Document Number: 001-66236 Rev. ** PRELIMINARY ® PSoC 5: CY8C52 Family Datasheet Figure 7-2. PSoC Creator Framework Page [+] Feedback [+] Feedback [+] Feedback ...
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Component Catalog Figure 7-3. Component Catalog The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device populated with an impressive selection of content; from simple primitives such as ...
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PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity. ...
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Input Muxes Input from Programmable Routing 6 PI Parallel Input/Output (To/From Programmable Routing) PO 7.2.2.6 Working Registers The datapath contains six primary working registers, which are accessed by CPU firmware or DMA during normal operation. Table 7-1. Working Datapath Registers ...
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Conditionals Each datapath has two compares, with bit masking options. Compare operands include the two accumulators and the two data registers in a variety of configurations. Other conditions include zero detect, all ones detect, and overflow. These conditions are ...
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UDB Array Description Figure 7-11 shows an example UDB array. In addition to the array core, there are a DSI routing interfaces at the top and bottom of the array. Other interfaces that are not explicitly ...
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Figure 7-13. Digital System Interconnect Timer Interrupt DMA CAN I2C Counters Controller Controller Digital System Routing I/F UDB ARRAY Digital System Routing I/F Global IO Port SC/CT EMIF Del-Sig Clocks Pins Blocks Interrupt and DMA routing is very flexible in ...
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CAN The CAN peripheral is a fully functional controller area network (CAN) supporting communication baud rates Mbps. The CAN controller implements the CAN2.0A and CAN2.0B specifications as defined in the Bosch specification and conforms to the ...
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Tx Buffer Status TxReq Pending TxInterrupt Request (if enabled) RxMessage0 Acceptance Code 0 Rx Buffer Status RxMessage RxMessage1 Acceptance Code 1 Available RxMessage14 Acceptance Code 14 RxInterrupt RxMessage15 Acceptance Code 15 Request (if enabled) 7.6 USB PSoC includes a dedicated ...
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Timers, Counters, and PWMs The Timer/Counter/PWM peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. As almost all embedded systems use some combination of timers, counters, and PWMs. Four of them have been ...
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SDA SCL START ADDRESS R/W Condition 8. Analog Subsystem The analog programmable system creates application specific combinations of both standard and advanced analog signal processing blocks. These blocks are then interconnected to each other and also ...
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The PSoC Creator software program provides a user-friendly interface to configure the analog connections between the GPIO and various analog resources and also connections from one analog resource to another. PSoC Creator also provides component libraries that allow you to ...
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ExVrefL ExVrefL1 opamp0 opamp2 swinp GPIO swfol swfol P0[4] swinn GPIO P0[5] GPIO * i0 abuf_vref_int P0[6] (1.024V) GPIO i2 * P0[7] cmp0_vref (1.024V) GPIO cmp_muxvn[1:0] P4[2] vref_cmp1 cmp1_vref (0.256V) bg_vda_res_en GPIO Vdda Vdda/2 ...
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Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in CY8C38, four in the left half (abusl [0:3]) and four in the ...
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From Analog Routing 8.3.2 LUT The CY8C52 family of devices contains two LUTs. The LUT is a two input, one output lookup table that is driven by one or two of the comparators in the chip. The output of any ...
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Ability to invert LCD display for negative image Three LCD driver drive modes, allowing power optimization LCD driver configurable to be active when PSoC is in limited active mode Figure 8-5. LCD System LCD Global DAC Clock UDB LCD Driver ...
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Reference Source 8.7.1 Current DAC The IDAC can be configured for the ranges µ 256 µA, and 0 to 2.048 mA. The IDAC can be configured to source or sink current. 8.7.2 Voltage DAC For ...
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Note that, while the debug interface at reset is always SWD, any standard SWD or JTAG debugging tool can switch from SWD to 4-pin JTAG or vice versa without requiring port acquisition, using a standard sequence defined by ARM. When ...
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If the device is protected with a WOL setting, Cypress cannot perform failure analysis and, therefore, cannot accept RMAs from customers. The WOL can be read out via Serial Wire Debug (SWD) port to electrically identify protected parts. You can ...
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Electrical Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, ...
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Device Level Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description V Analog supply voltage and input to DDA analog ...
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Table 11-2. DC Specifications (continued) Parameter Description [18] Hibernate Mode Hibernate mode current All regulators and oscillators off. SRAM retention GPIO interrupts are active Boost = OFF SIO pins in single ended input, unregulated output mode [19] Table 11-3. AC ...
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Power Regulators Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description V Input voltage DDD V Output voltage ...
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Inductive Boost Regulator. Table 11-6. Inductive Boost Regulator DC Specifications Unless otherwise specified, operating conditions are µF || 0.1 µF BOOST Parameter Description V Input voltage BAT Includes startup [20, 21] I Load current OUT ...
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Table 11-8. Recommended External Components for Boost Circuit Parameter Description L Boost inductor BOOST [24] C Filter capacitor BOOST I External Schottky F diode average forward current V R Figure 11-4. Efficiency vs V OUT mA, V ...
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Figure 11-8. Efficiency vs Switching Frequency OUT BAT OUT 11.1 Inputs and Outputs Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except ...
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Figure 11-9. GPIO Output High Voltage and Current Table 11-10. GPIO AC Specifications Parameter Description TriseF Rise time in Fast Strong Mode TfallF Fall time in Fast Strong Mode TriseS Rise time in Slow Strong Mode TfallS Fall time in ...
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SIO Table 11-11. SIO DC Specifications Parameter Description Vinmax Maximum input voltage Vinref Input voltage reference (Differential input mode) Output voltage reference (Regulated output mode) Voutref Input voltage high threshold V GPIO mode IH [26] Differential input mode Input ...
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Figure 11-13. SIO Output High Voltage and Current, Unregulated Mode Figure 11-15. SIO Output High Voltage and Current, Regulat- ed Mode Table 11-12. SIO AC Specifications Parameter Description TriseF Rise time in Fast Strong Mode [28] (90/10%) TfallF Fall time ...
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Table 11-12. SIO AC Specifications (continued) Parameter Description SIO output operating frequency 2.7 V < V < 5.5 V, Unregulated DDIO output (GPIO) mode, fast strong drive mode 1.71 V < V < 2.7 V, Unregu- DDIO lated output (GPIO) ...
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USBIO For operation in GPIO mode, the standard range for V Table 11-13. USBIO DC Specifications Parameter Description Rusbi USB D+ pull-up resistance Rusba USB D+ pull-up resistance Vohusb Static output high Volusb Static output low Vihgpio Input voltage ...
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Table 11-14. USBIO AC Specifications Parameter Description Tdrate Full-speed data rate average bit rate Tjr1 Receiver data jitter tolerance to next transition Tjr2 Receiver data jitter tolerance to pair transition Tdj1 Driver differential jitter to next transition Tdj2 Driver differential ...
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Table 11-15. USB Driver AC Specifications Parameter Description Tr Transition rise time Tf Transition fall time TR Rise/fall time matching Vcrs Output signal crossover voltage 11.1.4 XRES Table 11-16. XRES DC Specifications Parameter Description V Input voltage high threshold IH ...
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Analog Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.2.1 Voltage Reference Table 11-18. Voltage Reference Specifications Parameter Description V Precision reference voltage REF [30] Temperature drift Long term ...
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Analog Globals Table 11-21. Analog Globals AC Specifications Parameter Description Rppag Resistance pin-to-pin through [32] analog global Rppmuxbus Resistance pin-to-pin through [32] analog mux bus 11.2.4 Comparator Table 11-22. Comparator DC Specifications Parameter Description Input offset voltage in fast ...
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Current Digital-to-analog Converter (IDAC) See the IDAC component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-24. IDAC DC Specifications Parameter Description Resolution I Output ...
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Table 11-24. IDAC DC Specifications (continued) Parameter Description I Operating current, code = 0 DD Figure 11-21. IDAC INL vs Input Code, Range = 255 µA, Source Mode Document Number: 001-66236 Rev. ** PRELIMINARY ® PSoC 5: CY8C52 Family Datasheet ...
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Figure 11-23. IDAC DNL vs Input Code, Range = 255 µA, Source Mode Figure 11-25. IDAC INL vs Temperature, Range = 255 µA, Fast Mode Document Number: 001-66236 Rev. ** PRELIMINARY ® PSoC 5: CY8C52 Family Datasheet Figure 11-24. IDAC ...
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Figure 11-27. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode Figure 11-29. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode Document Number: 001-66236 Rev. ** PRELIMINARY ® PSoC 5: CY8C52 ...
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Table 11-25. IDAC AC Specifications Parameter Description F Update rate DAC T Settling time to 0.5 LSB SETTLE Figure 11-31. IDAC Step Response, Codes 0x40 - 0xC0, 255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V Figure 11-33. ...
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Voltage Digital to Analog Converter (VDAC) See the VDAC component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-26. VDAC DC Specifications Parameter Description Resolution ...
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Figure 11-36. VDAC INL vs Temperature Mode Figure 11-38. VDAC Full Scale Error vs Temperature Mode Figure 11-40. VDAC Operating Current vs Temperature Mode, Slow Mode Document Number: 001-66236 Rev. ** PRELIMINARY ® PSoC ...
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Table 11-27. VDAC AC Specifications Parameter Description F Update rate DAC TsettleP Settling time to 0.1%, step 25% to 75% TsettleN Settling time to 0.1%, step 75% to 25% Figure 11-42. VDAC Step Response, Codes 0x40 - 0xC0 ...
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Temperature Sensor Table 11-28. Temperature Sensor Specifications Parameter Description Temp sensor accuracy 11.2.8 LCD Direct Drive Table 11-29. LCD Direct Drive DC Specifications Parameter Description I LCD system operating current CC I Current per segment driver CC_SEG V LCD ...
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Digital Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.3.1 Timer The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; ...
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Pulse Width Modulation The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented in UDBs; for more information, see the PWM component data sheet in PSoC Creator. Table 11-35. PWM DC Specifications ...
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USB Table 11-41. USB DC Specifications Parameter Description V Device supply for USB operation USB_5 V USB_3.3 V USB_3 I Device supply current in device active USB_Configured mode, bus clock and IMO = 24 MHz I Device supply current ...
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Memory Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.4.1 Flash Table 11-43. Flash DC Specifications Parameter Description Erase and program voltage Table 11-44. Flash AC Specifications Parameter Description T ...
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Table 11-46. EEPROM AC Specifications Parameter Description T Single row erase/write cycle time WRITE EEPROM endurance EEPROM data retention time 11.4.3 SRAM Table 11-47. SRAM DC Specifications Parameter Description V SRAM retention voltage SRAM Table 11-48. SRAM AC Specifications Parameter ...
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Voltage Monitors Table 11-51. Voltage Monitors DC Specifications Parameter Description LVI Trip voltage LVI_A/D_SEL[3:0] = 0000b LVI_A/D_SEL[3:0] = 0001b LVI_A/D_SEL[3:0] = 0010b LVI_A/D_SEL[3:0] = 0011b LVI_A/D_SEL[3:0] = 0100b LVI_A/D_SEL[3:0] = 0101b LVI_A/D_SEL[3:0] = 0110b LVI_A/D_SEL[3:0] = 0111b LVI_A/D_SEL[3:0] = ...
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JTAG Interface Table 11-54. JTAG Interface AC Specifications Parameter Description f_TCK TCK frequency T_TDI_setup TDI setup before TCK high T_TMS_setup TMS setup before TCK high T_TDI_hold TDI, TMS hold after TCK high T_TDO_valid TCK low to TDO valid T_TDO_hold ...
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Clocking Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. Unless otherwise specified, all charts and graphs show typical values. 11.6.1 32 kHz External Crystal Table 11-57. 32 kHz External Crystal ...
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Table 11-60. IMO AC Specifications (continued) Parameter Description [41] Startup time [41] Jitter (peak to peak) Jp MHz MHz [41] Jitter (long term) Jperiod MHz MHz Figure 11-56. ...
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Internal Low Speed Oscillator Table 11-61. ILO DC Specifications Parameter Description Operating current I CC Leakage current Table 11-62. ILO AC Specifications Parameter Description Startup time, all frequencies ILO frequencies (trimmed) 100 kHz 1 kHz F ILO ILO frequencies ...
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Phase-Locked Loop Table 11-65. PLL DC Specifications Parameter Description I PLL operating current DD Table 11-66. PLL AC Specifications Parameter Description [43] Fpllin PLL input frequency PLL intermediate frequency [43] Fpllout PLL output frequency Lock time at startup [45] ...
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... SAR CY8C5247LTI-089 40 128 32 2 ✔ 1x12-bit SAR ✔ CY8C5247AXI-051 40 128 32 2 1x12-bit SAR ✔ CY8C5246LTI-029 1x12-bit SAR CY8C5246AXI-054 ✔ 1x12-bit SAR 12.1 Part Numbering Conventions PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric ( … … ...
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Examples 5: PSoC 5 5: CY8C55 Family 8: 80 MHz 8: 256 KB AX: TQFP I: Industrial All devices in the PSoC 5 CY8C52 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free products. Lead (Pb) is ...
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Figure 13-1. 68-pin QFN 8x8 with 0.4 mm Pitch Package Outline (Sawn Version) Figure 13-2. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline Document Number: 001-66236 Rev. ** PRELIMINARY ® PSoC 5: CY8C52 Family Datasheet 001-09618 *C 51-85048 ...
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Acronyms Table 14-1. Acronyms Used in this Document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus archi- tecture) high-performance bus, an ARM data transfer bus ALU arithmetic logic unit AMUXBUS ...
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Table 14-1. Acronyms Used in this Document (continued) Acronym Description PICU port interrupt control unit PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration data sheet POR power-on reset PRES precise ...
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Document Conventions 16.1 Units of Measure Table 16-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz kΩ kilohms ksps kilosamples ...
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PRELIMINARY 17. Revision History ® Description Title: PSoC 5: CY8C52 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-66236 Submission Rev. ECN No. Date ** 3198501 03/17/2011 18. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a ...