DP83848K_08 NSC [National Semiconductor], DP83848K_08 Datasheet - Page 55
DP83848K_08
Manufacturer Part Number
DP83848K_08
Description
Manufacturer
NSC [National Semiconductor]
Datasheet
1.DP83848K_08.pdf
(78 pages)
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Bit
4:0
5
PHYADDR[4:0]
LED_CNFG[0]
Bit Name
Table 27. PHY Control Register (PHYCR), address 0x19 (Continued)
Strap, RW
Strap, RW
Default
LED Configuration
In Mode 1, LEDs are configured as follows:
LED_LINK = ON for Good Link, OFF for No Link
LED_SPEED = ON in 100Mb/s, OFF in 10Mb/s
In Mode 2, LEDs are configured as follows:
LED_LINK = ON for good Link, BLINK for Activity
LED_SPEED = ON in 100Mb/s, OFF in 10Mb/s
PHY Address: PHY address for port.
LED_ CNFG[0]
55
1
0
Mode Description
Description
Mode 1
Mode2
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