DP83848K_08 NSC [National Semiconductor], DP83848K_08 Datasheet - Page 68
![no-image](/images/no-image-200.jpg)
DP83848K_08
Manufacturer Part Number
DP83848K_08
Description
Manufacturer
NSC [National Semiconductor]
Datasheet
1.DP83848K_08.pdf
(78 pages)
- Current page: 68 of 78
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8.2.11 10 Mb/s MII Transmit Timing
Note: An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII
signals are sampled on the falling edge of TX_CLK.
8.2.12 10 Mb/s MII Receive Timing
Note: RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Min-
imum high and low times will not be violated.
T2.11.1
T2.11.2
T2.11.3
T2.12.1
T2.12.2
T2.12.3
Parameter
Parameter
RX_CLK
RXD[3:0]
RX_DV
TX_CLK High/Low Time
TXD[3:0], TX_EN Data Setup to TX_CLK fall
TXD[3:0], TX_EN Data Hold from TX_CLK rise
RX_CLK High/Low Time
RX_CLK to RXD[3:0], RX_DV Delay
RX_CLK rising edge delay from RXD[3:0],
RX_DV Valid
TXD[3:0]
TX_CLK
TX_EN
Description
Description
T2.11.1
T2.11.2
T2.12.1
T2.12.2
Valid Data
68
Valid Data
10 Mb/s MII mode
10 Mb/s MII mode
T2.12.3
10 Mb/s MII mode
10 Mb/s MII mode
10 Mb/s MII mode
Notes
Notes
T2.12.1
T2.11.1
T2.11.3
Min
160
100
100
Min
190
25
0
Typ
200
Typ
200
Max
240
Max Units
210
Units
ns
ns
ns
ns
ns
ns
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