PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 128
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PIC18C658
Manufacturer Part Number
PIC18C658
Description
High-Performance Microcontrollers with CAN Module
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18C658.pdf
(366 pages)
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PIC18CXX8
14.1
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
14.2
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
TABLE 14-1:
TABLE 14-2:
DS30475A-page 128
CCPx Mode CCPy Mode
Capture
Capture
Compare
PWM
PWM
PWM
CCP Mode
Compare
CCP1 Module
CCP2 Module
Capture
PWM
Capture
Compare
Compare
PWM
Capture
Compare
CCP MODE - TIMER
RESOURCE
INTERACTION OF TWO CCP MODULES
TMR1 or TMR3 time-base. Time-base can be different for each CCP.
The compare could be configured for the special event trigger, which clears either TMR1
or TMR3, depending upon which time-base is used.
The compare(s) could be configured for the special event trigger, which clears TMR1 or
TMR3 depending upon which time-base is used.
The PWMs will have the same frequency and update rate (TMR2 interrupt).
None
None
Timer1 or Timer3
Timer1 or Timer3
Timer Resource
Timer2
Advanced Information
14.3
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 or TMR3 registers when an
event occurs on pin RC2/CCP1. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR registers) is set. It
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old cap-
tured value will be lost.
14.3.1
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
14.3.2
The timers used with the capture feature (either Timer1
and/or Timer3) must be running in Timer mode or Syn-
chronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer
used with each CCP module is selected in the T3CON
register.
Note:
Interaction
Capture Mode
CCP PIN CONFIGURATION
TIMER1/TIMER3 MODE SELECTION
If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
2000 Microchip Technology Inc.
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