PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 52
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PIC18C658
Manufacturer Part Number
PIC18C658
Description
High-Performance Microcontrollers with CAN Module
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18C658.pdf
(366 pages)
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PIC18CXX8
TABLE 4-3:
DS30475A-page 52
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
Legend:
Note 1:
Filename
2:
3:
4:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset.
These registers are reserved on PIC18C658.
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH
RBPU
INT2IP
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register)
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value
of FSR0 offset by WREG
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value
of FSR1 offset by WREG
Indirect Data Memory Address Pointer 1 Low Byte
STKFUL
Bit 7
—
—
—
—
—
—
REGISTER FILE SUMMARY
PEIE/GIEL
INTEDG0
STKUNF
INT1IP
Bit 6
—
—
—
—
—
—
INTEDG1
TMR0IE
bit 21
bit 21
INT3IE
Bit 5
—
—
—
—
—
(3)
(2)
Advanced Information
Top-of-Stack upper Byte (TOS<20:16>)
Return Stack Pointer
Holding Register for PC<20:16>
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INTEDG2
INT0IE
INT2IE
Bit 4
—
—
—
Indirect Data Memory Address Pointer 0 High
Indirect Data Memory Address Pointer 1 High
Bank Select Register
INTEDG3
INT1IE
RBIE
Bit 3
TMR0IF
TMR0IP
INT3IF
Bit 2
INT3IP
INT0IF
INT2IF
Bit 1
2000 Microchip Technology Inc.
INT1IF
RBIF
RBIP
Bit 0
---0 0000
0000 0000
0000 0000
00-0 0000
--00 0000
0000 0000
0000 0000
---0 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 1111
1100 0000
---- 0000
xxxx xxxx
xxxx xxxx
---- 0000
xxxx xxxx
---- 0000
Value on
POR,
BOR
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
---0 0000
0000 0000
0000 0000
00-0 0000
--00 0000
0000 0000
0000 0000
---0 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 1111
1100 0000
---- 0000
uuuu uuuu
uuuu uuuu
---- 0000
uuuu uuuu
---- 0000
RESETS
Value on
all other
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
(3)
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