PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 94

• Manufacturer Part Number: PIC18F1230
• Description: 18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1230/1330
10.2
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2 and PIR3).
REGISTER 10-4:
DS39758B-page 92
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
PIR Registers
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty
TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full
CMP2IF: Analog Comparator 2 Flag bit
1 = The output of CMP2 has changed since last read
0 = The output of CMP2 has not changed since last read
CMP1IF: Analog Comparator 1 Flag bit
1 = The output of CMP1 has changed since last read
0 = The output of CMP1 has not changed since last read
CMP0IF: Analog Comparator 0 Flag bit
1 = The output of CMP0 has changed since last read
0 = The output of CMP0 has not changed since last read
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
R/W-0
ADIF
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
W = Writable bit
‘1’ = Bit is set
RCIF
R-0
Advance Information
TXIF
R-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CMP2IF
R/W-0
Note 1: Interrupt flag bits are set when an interrupt
2: User
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
CMP1IF
R/W-0
software
© 2006 Microchip Technology Inc.
x = Bit is unknown
CMP0IF
R/W-0
should
ensure
TMR1IF
R/W-0
bit 0
the