DP83932C NSC [National Semiconductor], DP83932C Datasheet - Page 42

• Manufacturer Part Number: DP83932C
• Description: MHz SONICTM Systems-Oriented Network Interface Controller
• Manufacturer: NSC [National Semiconductor]

4 0 SONIC Registers
4 3 12 General Purpose Timer
The SONIC contains a 32-bit general-purpose Watchdog
Timer for timing user-definable events This timer is ac-
cessed by the user through two 16-bit read write registers
(WT1 and WT0) The lower count value is programmed
through the WT0 register and the upper count value is pro-
grammed through the WT1 register
These two registers are concatenated together to form the
complete 32-bit timer This timer clocked at
Clock (TXC) frequency counts down from its programmed
value and generates an interrupt if enabled (Interrupt Mask
register) when it rolls over from 0000 0000h to FFFF
FFFFh When the counter rolls over it continues decrement-
ing unless explicitly stopped (setting the STP bit) The timer
is controlled by the ST (Start Timer) and STP (Stop Timer)
bits in the Command register A hardware or software reset
halts but does not clear the General Purpose timer
4 3 13 Silicon Revision Register
This is a 16-bit read only register It contains information on
the current revision of the SONIC The value of the
DP83932CVF revision register is 6h
5 0 Bus Interface
SONIC features a high speed non-multiplexed address and
data bus designed for a wide range of system environments
The data bus can be programmed (via the Data Configura-
tion Register) to a width of either 32- or 16-bits SONIC con-
31
WT1 (Upper Count Value)
16
15
WT0 (Lower Count Value)
(Continued)
the Transmit
0
42
tains an on-chip DMA and supplies all the necessary signals
for DMA operation With 31 address lines SONIC can ac-
cess a full 2 G-word address space To accommodate dif-
ferent memory speeds wait states can be added to the bus
cycle by two methods The memory subsystem can add wait
states by simply withholding the appropriate handshake sig-
nals In addition the SONIC can be programmed (via the
Data Configuration Register) to add wait states
The SONIC is designed to interface to both the National In-
tel and Motorola style buses To facilitate minimum chip
count designs and complete bus compatibility the user can
program the SONIC for the following bus modes
The mode pin (BMODE) along with the SBUS bit in the Data
Configuration Register are used to select the bus mode
This section describes the SONIC’s pin signals provides
system interface examples and describes the various
SONIC bus operations
5 1 PIN CONFIGURATIONS
There are two user selectable pin configurations for SONIC
to provide the proper interface signals for either the Nation-
al Intel or Motorola style buses The state of the BMODE
pin is used to define the pin configuration Figure 5-1 shows
the pin configuration when BMODE
Motorola style bus Figure 5-2 shows the pin configuration
when BMODE
style bus
National Intel bus operating in synchronous mode
National Intel bus operating in asynchronous mode
Motorola bus operating in synchronous mode
Motorola bus operating in asynchronous mode
e
0 (tied to ground) for the National Intel
e
1 (tied to V
CC
) for the