DP83932C NSC [National Semiconductor], DP83932C Datasheet - Page 58

• Manufacturer Part Number: DP83932C
• Description: MHz SONICTM Systems-Oriented Network Interface Controller
• Manufacturer: NSC [National Semiconductor]

5 0 Bus Interface
5 4 5 3 Memory Cycle for BMODE
Asynchronous Mode
On the rising edge of T1 the SONIC asserts ECS to indicate
that the memory cycle is starting The address (A31-A1)
bus status (S2-S0) and the direction strobe (MRW) are driv-
en and do not change for the remainder of the memory
cycle On the falling edge of T1 the SONIC deasserts ECS
and asserts AS
In asynchronous mode DSACK0 1 are asynchronously
sampled on the falling edge of both T1 and T2 DSACK0 1
FIGURE 5-10 Memory Read BMODE
FIGURE 5-11 Memory Read BMODE
(Continued)
e
1
58
e
e
do not need to be synchronized to the bus clock because
the chip always resolves these signals to either a high or
low state If a synchronous termination of the bus cycle is
required however STERM may be used STERM is sam-
pled on the rising edge of T2 and must meet the setup and
hold times with respect to that edge for proper operation
Meeting the setup time for DSACK0 1 or STERM guaran-
tees that the SONIC will terminate the memory cycle 1 5
1 Asynchronous (1 Wait-State)
1 Asynchronous (2 Wait-State)
TL F 10492 – 36
TL F 10492 – 37