DP83936AVF NSC [National Semiconductor], DP83936AVF Datasheet - Page 79
DP83936AVF
Manufacturer Part Number
DP83936AVF
Description
Full Duplex SONICTM-T Systems-Oriented Network Interface Controller with Twisted Pair Interface
Manufacturer
NSC [National Semiconductor]
Datasheet
1.DP83936AVF.pdf
(104 pages)
- Current page: 79 of 104
- Download datasheet (2Mb)
Number
T9
T11
T11b
T12
T12b
T15
T32
T33
T36
T37
9 0 AC and DC Specifications
MEMORY WRITE BMODE
Note 1 For successive read operations MWR remains high
Note 2 One idle clock cycle (Ti) will be inserted between the last write cycle and the following read cycle in RDA and TDA operation Note that the data bus will
become TRI-STATE from the rising edge of the clock after the idle cycle (see T52 for BSCK to data TRI-STATE timing)
BSCK to Address Valid Hold Time
BSCK to ADS Low
BSCK to ECS Low
BSCK to ADS High
BSCK to ECS High
ADS High Width
RDYi Setup to BSCK
RDYi Hold from BSCK
BSCK to Memory Write Data Valid Hold Time
(Note 2)
BSCK to MWR (Write) Valid (Note 1)
e
0 SYNCHRONOUS MODE (one wait-state shown)
Parameter
(Continued)
79
Min
45
19
3
5
3
20 MHz
Max
26
19
24
29
26
50
24
Min
35
17
3
3
3
25 MHz
Max
24
17
22
27
48
22
24
Min
25
15
3
3
3
33 MHz
http
Max
TL F 12597 – 60
22
15
20
25
46
20
22
www national com
Units
ns
ns
ns
ns
ns
ns
ns
ns
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