PIC18F2221 MICROCHIP [Microchip Technology], PIC18F2221 Datasheet - Page 87
PIC18F2221
Manufacturer Part Number
PIC18F2221
Description
28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2221.pdf
(396 pages)
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7.2
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available on the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another read operation, or until it is written to
by the user (during a write operation).
The basic process is shown in Example 7-1.
7.3
To write an EEPROM data location, the address must
first be written to the EEADR register and the data
written to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
EXAMPLE 7-1:
EXAMPLE 7-2:
© 2007 Microchip Technology Inc.
Required
Sequence
Reading the Data EEPROM
Memory
Writing to the Data EEPROM
Memory
MOVLW
MOVWF
BCF
BCF
BSF
MOVF
DATA_EE_ADDR
EEADR
EECON1, EEPGD
EECON1, CFGS
EECON1, RD
EEDATA, W
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
DATA EEPROM READ
DATA EEPROM WRITE
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
EECON1, EPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
;
; Data Memory Address to read
; Point to DATA memory
; Access EEPROM
; EEPROM Read
; W = EEDATA
Preliminary
;
; Data Memory Address to write
;
; Data Memory Value to write
; Point to DATA memory
; Access EEPROM
; Enable writes
; Disable Interrupts
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Enable Interrupts
; User code execution
; Disable writes on write complete (EEIF set)
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared by
hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag
bit, EEIF, is set. The user may either enable this
interrupt, or poll this bit. EEIF must be cleared by
software.
7.4
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
PIC18F4321 FAMILY
Write Verify
DS39689E-page 85
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