PLDC20RA10-15JC CYPRESS [Cypress Semiconductor], PLDC20RA10-15JC Datasheet - Page 2

• Manufacturer Part Number: PLDC20RA10-15JC
• Description: Reprogrammable Asynchronous CMOS Logic Device
• Manufacturer: CYPRESS [Cypress Semiconductor]

Selection Guide
Pin Configurations
Macrocell Architecture
Figure 1 illustrates the architecture of the 20RA10 macrocell.
The cell dedicates three product terms for fully asynchronous
control of the register set, reset, and clock functions, as well
as, one term for control of the output enable function.
The output enable product term output is ANDed with the input
from pin 13 to allow either product term or hardwired external
control of the output or a combination of control from both
sources. If product-term-only control is selected, it is automat-
ically chosen for all outputs since, for this case, the external
output enable pin must be tied LOW. The active polarity of
each output may be programmed independently for each out-
put cell and is subsequently fixed. Figure 2 illustrates the out-
put enable options available.
When an I/O cell is configured as an output, combinatorial-only
capability may be selected by forcing the set and reset product
term outputs to be HIGH under all input conditions. This is
achieved by programming all input term programming cells for
these two product terms. Figure 3 illustrates the available out-
put configuration options.
An additional four uncommitted product terms are provided in
each output macrocell as resources for creation of user-de-
fined logic functions.
Programmable I/O
Because any of the ten I/O pins may be selected as an input,
the device input configuration programmed by the user may
vary from a total of nine programmable plus ten dedicated in-
puts (a total of nineteen inputs) and one output down to a
ten-input, ten-output configuration with all ten programmable
I/O cells configured as outputs. Each input pin available in a
given configuration is available as an input to the four control
Note:
Document #: 38-03012 Rev. **
1.
20RA10-15
20RA10-20
20RA10-25
20RA10-35
Generic Part
Number
The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The
principal difference is in the location of the “no connect” (NC) pins
NC
I
I
I
I
I
I
2
3
4
5
6
7
5
6
7
8
9
10
11
PLDC20RA10
12131415161718
4 3 2
Top View
LCC
1
Com‘l
282726
15
20
25
24
23
22
21
20
19
t
RA10–2
PD
NC
I/O
I/O
I/O
I/O
I/O
I/O
ns
2
3
4
5
6
7
Mil
20
25
35
NC
NC
NC
I 3
I
I
I 6
4
5
Com’l
STD PLCC/HLCC
5
6
7
8
9
10
11
10
7
121314 1516 1718
4 3 2
PLDC20RA10
Top View
t
SU
1
ns
2827 26
Mil
10
15
20
25
24
23
22
21
20
19
product terms and four uncommitted product terms of each
programmable I/O macrocell that has been configured as an
output.
An I/O cell is programmed as an input by tying the output en-
able pin (pin 13) HIGH or by programming the output enable
product term to provide a LOW, thereby disabling the output
buffer, for all possible input combinations.
When utilizing the I/O macrocell as an output, the input path
functions as a feedback path allowing the output signal to be
fed back as an input to the product term array. When the output
cell is configured as a registered output, this feedback path
may be used to feed back the current output state to the device
inputs to provide current state control of the next output state
as required for state machine implementation.
Preload and Power-Up Reset
Functional testability of programmed devices is enhanced by
inclusion of register preload capability, which allows the state
of each register to be set by loading each register from an
external source prior to exercising the device. Testing of com-
plex state machine designs is simplified by the ability to load
an arbitrary state without cycling through long test vector se-
quences to reach the desired state. Recovery from illegal
states can be verified by loading illegal states and observing
recovery. Preload of a particular register is accomplished by
impressing the desired state on the register output pin and
lowering the signal level on the preload control pin (pin1) to a
logic LOW level. If the specified preload set-up, hold and pulse
width minimums have been observed, the desired state is
loaded into the register. To insure predictable system initializa-
tion, all registers are preset to a logic LOW state upon pow-
er-up, thereby setting the active LOW outputs to a logic HIGH.
I/O
I/O
I/O
I/O
I/O
I/O
NC
RA10–3
2
3
4
5
6
7
Com’l
15
20
t
CO
NC
I 2
I 3
I
I
I 6
I 7
4
5
JEDEC PLCC/HLCC
ns
5
6
7
8
9
10
11
Mil
20
25
35
121314 1516 1718
4 3 2
PLDC20RA10
Top View
CG7C324
1
2827 26
Com’l
80
80
PLDC20RA10
25
24
23
22
21
20
19
[1]
I/O
I/O
I/O
NC
I/O
I/O
I/O
t
CC
2
3
4
5
6
7
ns
Page 2 of 14
RA10–4
Mil
85
85
85